LG 65LA970T-DA (CHASSIS:LT34E) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
D13_SPI_DO_M
D13_SPI_SCLK_M
D13_SPI_DI_M
D13_HDMI_TX0N
D13_HDMI_TX0P
D13_HDMI_TX1N
D13_HDMI_TX1P
D13_HDMI_TXCN
D13_HDMI_TXCP
D13_HDMI_TX2N
D13_HDMI_TX2P
D13_STPO_CLK
D13_STPO_SOP
D13_STPO_VAL
D13_STPO_ERR
D13_STPO_DATA
XTAL_OUT
XTAL_IN
R12007
1M
1M
XTAL_OUT
XTAL_IN
SPI_DL_MODE
+3.3V_NORMAL
3.3K
R12016
D13_TDO_1
D13_TDI_1
P12000
12507WS-08L
HEVC_DEBUG
1
2
3
4
5
6
7
8
9
+3.3V_NORMAL
D13_TRST_N_1
C12001
0.1uF
16V
0.1uF
16V
HEVC_DEBUG
R12004
33
HEVC_DEBUG
R12003
33
HEVC_DEBUG
R12002
33
HEVC_DEBUG
R12000
33
HEVC_DEBUG
R12001
33
HEVC_DEBUG
D13_TCK_1
D13_TMS_1
D13_UART_RX_1
D13_UART_TX_1
P12001
12507WS-04L
HEVC_DEBUG
1
2
3
4
5
+3.3V_NORMAL
R12006
33
HEVC_DEBUG
R12005
33
HEVC_DEBUG
C12002
0.1uF
16V
0.1uF
16V
HEVC_DEBUG
D13_SPI_CS/GPIO[0]
R12018
10K
10K
OPT
R12015
0
0
1/16W
5%
5%
D13_SPI_DO_M
D13_SPI_DI_M
C12005
0.1uF
0.1uF
D13_FLASH_WP
D13_SPI_SCLK_M
R12032
3.3K
R12017
10K
IC12001
MX25L3206EM2I-12G
3
WP#
2
SO/SIO1
4
GND
1
CS#
5
SI/SIO0
6
SCLK
7
HOLD#
8
VCC
R12019
33
+3.3V_NORMAL
D13_SPI_CS/GPIO[0]
R12010
10K
+3.3V_NORMAL
R12011
10K
OPT
D13_UART_RX_1
D13_UART_RX_0
D13_UART_TX_1
D13_UART_TX_0
D13_TMS_1
D13_TCK_0
D13_TCK_1
D13_TMS_0
D13_TDI_0
D13_TDI_1
D13_TRST_N_0
D13_TDO_0
D13_TRST_N_1
D13_TDO_1
R12027
33
R12026
33
R12025
33
SOC_SPI0_MOSI
SOC_SPI0_MISO
D13_TMS_0
D13_TDI_0
D13_TCK_0
D13_TRST_N_0
D13_TDO_0
D13_UART_TX_0
D13_UART_RX_0
R12037
1.6K 1%
D13_HDMI_DDC_DA
D13_HDMI_HPD
D13_HDMI_DDC_CK
R12024
33
SOC_SPI0_SCLK
SOC_SPI0_CS0
R12028
33
OPT
R12030
33
OPT
I2C_SCL2
R12029
33
OPT
R12031
33
OPT
I2C_SDA2
D13_SPI_CS/GPIO[0]
C12004
0.01uF
D13_FLASH_WP
I2C_SDA2
D13_SPI_SCLK_M
R12046
0
HEVC_DEBUG
+3.3V_NORMAL
R12039
0
HEVC_DEBUG
I2C_SCL2
R12043
1K
HEVC_DEBUG
R12038
0
HEVC_DEBUG
D13_SPI_DI_M
R12042
0
HEVC_DEBUG
P12002
12507WS-10L
HEVC_DEBUG
1
2
3
4
5
6
7
8
9
10
11
R12044
0
OPT
R12040
0
HEVC_DEBUG
R12047
0
HEVC_DEBUG
R12041
0
HEVC_DEBUG
SPI_DL_MODE
R12045
0
OPT
D13_SPI_CS/GPIO[0]
D13_SPI_DO_M
D13_FLASH_WP
X12000
24.75MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
C12003
27pF
50V
27pF
50V
C12000
27pF
50V
27pF
50V
D13_RESET
R12008
33
R12012
33
R12022
33
R12023
33
R12033
33
C12261
10pF
10pF
R12014
33
D13_SMODE[0]
D13_SMODE[1]
R12013
10K
+3.3V_NORMAL
R12021
10K
R12009
10K
OPT
D13_SMODE[1]
+3.3V_NORMAL
D13_SMODE[0]
R12020
10K
OPT
+3.3V_NORMAL
R12034
3.3K
R12035
3.3K
R12036
3.3K
OPT
R12048
3.3K
D13_INT
R12049
10
10
33
R12050
R12051
33
IC12000
LG1153
HEVC
XTALI
R2
XTALO
R1
PORES_N
A18
TRST_N0
E1
TMS0
C3
TCK0
D1
TDI0
B1
TDO0
D3
TRST_N1
E2
TMS1
B3
TCK1
D2
TDI1
B2
TDO1
C2
UART_RXD0
B10
UART_TXD0
A10
UART_RXD1
B9
UART_TXD1
A9
SPI_SCLK_S
C20
SPI_CS_S
D20
SPI_DO_S
D19
SPI_DI_S
C19
SPI_SCLK_M
A14
SPI_CS_M
B14
SPI_DO_M
B13
SPI_DI_M
A13
SCL_S
A11
SDA_S
B11
SCL_M
A12
SDA_M
B12
STPI_CLK
G20
STPI_SOP
H19
STPI_VAL
G19
STPI_ERR
H20
STPI_DATA[0]
J19
STPI_DATA[1]
J20
STPI_DATA[2]
K19
STPI_DATA[3]
K20
STPI_DATA[4]
L19
STPI_DATA[5]
L20
STPI_DATA[6]
M19
STPI_DATA[7]
M20
GPIO[7]
B7
GPIO[6]
A7
GPIO[5]
B6
GPIO[4]
A6
GPIO[3]
B5
GPIO[2]
A5
GPIO[1]
B4
GPIO[0]
A4
HDMI_DDC_CK
G1
HDMI_DDC_DA
G2
HDMI_HPD
J2
HDMI_REXT
J1
HDMI_CEC
H2
HDMI_DDCCEC
H1
HDMI_TX0N
M1
HDMI_TX0P
M2
HDMI_TX1N
L1
HDMI_TX1P
L2
HDMI_TX2N
K1
HDMI_TX2P
K2
HDMI_TXCN
N1
HDMI_TXCP
N2
SMODE[0]
F2
SMODE[1]
E3
TMODE[0]
A16
TMODE[1]
B16
TMODE[2]
A17
TMODE[3]
B17
XTAL(24.75MHz)
JTAG for HEVC
UART For HEVC
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
SPI FLASH(4MByte)
GPIO[0]
- 1 : Serial Flash Boot
- 0 : Live Boot
- 1 : Serial Flash Boot
- 0 : Live Boot
Closed to D13
Serial Flash Boot Test
HEVC option sheet
SMODE[1:0]
- 00 : Normal Mode
- Other : Test Mode
- 00 : Normal Mode
- Other : Test Mode
H/W Option : default low
SPI Clock Frq. &
DDR density
(High:512MB, LOW:256MB)
SPI Clock Frq. &
DDR density
(High:512MB, LOW:256MB)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
D13_DDR_A[12]
D13_DDR_A[11]
D13_DDR_A[10]
D13_DDR_A[9]
D13_DDR_A[8]
D13_DDR_A[7]
D13_DDR_A[6]
D13_DDR_A[5]
D13_DDR_A[4]
D13_DDR_A[3]
D13_DDR_A[2]
D13_DDR_A[1]
D13_DDR_A[0]
D13_DDR_A[0]
D13_DDR_A[1]
D13_DDR_A[2]
D13_DDR_A[3]
D13_DDR_A[4]
D13_DDR_A[5]
D13_DDR_A[6]
D13_DDR_A[7]
D13_DDR_A[8]
D13_DDR_A[9]
D13_DDR_A[10]
D13_DDR_A[11]
D13_DDR_A[12]
D13_DDR_A[0]
D13_DDR_A[1]
D13_DDR_A[2]
D13_DDR_A[3]
D13_DDR_A[4]
D13_DDR_A[5]
D13_DDR_A[6]
D13_DDR_A[7]
D13_DDR_A[8]
D13_DDR_A[9]
D13_DDR_A[10]
D13_DDR_A[11]
D13_DDR_A[12]
D13_DDR_DQ[15]
D13_DDR_DQ[14]
D13_DDR_DQ[13]
D13_DDR_DQ[12]
D13_DDR_DQ[11]
D13_DDR_DQ[10]
D13_DDR_DQ[9]
D13_DDR_DQ[8]
D13_DDR_DQ[7]
D13_DDR_DQ[6]
D13_DDR_DQ[5]
D13_DDR_DQ[4]
D13_DDR_DQ[3]
D13_DDR_DQ[2]
D13_DDR_DQ[1]
D13_DDR_DQ[0]
D13_DDR_DQ[0]
D13_DDR_DQ[1]
D13_DDR_DQ[2]
D13_DDR_DQ[3]
D13_DDR_DQ[4]
D13_DDR_DQ[5]
D13_DDR_DQ[6]
D13_DDR_DQ[7]
D13_DDR_DQ[8]
D13_DDR_DQ[9]
D13_DDR_DQ[10]
D13_DDR_DQ[11]
D13_DDR_DQ[12]
D13_DDR_DQ[13]
D13_DDR_DQ[14]
D13_DDR_DQ[15]
D13_DDR_DQ[16]
D13_DDR_DQ[17]
D13_DDR_DQ[18]
D13_DDR_DQ[19]
D13_DDR_DQ[20]
D13_DDR_DQ[21]
D13_DDR_DQ[22]
D13_DDR_DQ[23]
D13_DDR_DQ[24]
D13_DDR_DQ[25]
D13_DDR_DQ[26]
D13_DDR_DQ[27]
D13_DDR_DQ[28]
D13_DDR_DQ[29]
D13_DDR_DQ[30]
D13_DDR_DQ[31]
D13_DDR_DQ[18]
D13_DDR_DQ[19]
D13_DDR_DQ[20]
D13_DDR_DQ[21]
D13_DDR_DQ[22]
D13_DDR_DQ[23]
D13_DDR_DQ[24]
D13_DDR_DQ[25]
D13_DDR_DQ[26]
D13_DDR_DQ[27]
D13_DDR_DQ[28]
D13_DDR_DQ[29]
D13_DDR_DQ[30]
D13_DDR_DQ[31]
D13_DDR_DQ[17]
D13_DDR_DQ[16]
D13_DDR_A[13]
D13_DDR_A[13]
D13_DDR_A[13]
D13_DDR_DQ[0-15]
D13_DDR_DQS[0]
D13_DDR_DQ[0-15]
D13_DDR_DQ[16-31]
D13_DDR_A[0-13]
D13_DDR_DQS[0]
D13_DDR_DQS[1]
D13_DDR_DQS[1]
D13_DDR_DQS[2]
D13_DDR_DQS[2]
D13_DDR_DQS[3]
D13_DDR_DQS[3]
D13_DDR_DQS[1]
D13_DDR_DQS[1]
D13_DDR_DQS[0]
D13_DDR_DQS[0]
D13_DDR_DQS[2]
D13_DDR_DQS[3]
D13_DDR_DQS[2]
D13_DDR_DQS[3]
D13_DDR_BA[0]
D13_DDR_BA[1]
D13_DDR_BA[2]
D13_D1_CLK
D13_D1_CLK
D13_D0_CLK
D13_D0_CLK
D13_DDR_CKE
D13_DDR_RAS
D13_DDR_WE
D13_DDR_ODT
D13_DDR_CAS
D13_DDR_RESET
D13_DDR_DM[1]
D13_DDR_DM[3]
D13_DDR_DM[0]
D13_DDR_DM[2]
D13_DDR_BA[0]
D13_DDR_BA[1]
D13_DDR_BA[2]
D13_D0_CLK
D13_DDR_CKE
D13_D0_CLK
D13_DDR_RAS
D13_DDR_ODT
D13_DDR_CAS
D13_DDR_RESET
D13_DDR_WE
D13_DDR_DM[0]
D13_DDR_DM[1]
D13_D1_CLK
D13_DDR_RESET
D13_D1_CLK
D13_DDR_BA[0]
D13_DDR_ODT
D13_DDR_WE
D13_DDR_BA[2]
D13_DDR_BA[1]
D13_DDR_CKE
D13_DDR_RAS
D13_DDR_CAS
D13_DDR_DM[2]
D13_DDR_DM[3]
D13_DDR_DQ[16-31]
D13_DDR_A[0-13]
D13_DDR_A[0-13]
R12100
240
240
1%
R12114
240
240
1%
R12109
240
240
1%
C12100
0.1uF
R12104
1K
1%
D13_D1_CLK
R12108
10K
C12102
0.1uF
R12105
1K
1%
R12112
1K
1%
R12101
100
R12111
1K
1%
R12110
1K
1%
D13_D0_CLK
VDDC15_D13_DDR
C12101
0.1uF
R12107
1K
1%
R12106
1K
1%
C12103
0.1uF
D13_D1_CLK
D13_DDR_CKE
D13_D0_CLK
D13_DDR_RESET
R12102
10K
R12103
100
R12113
1K
1%
D13_DDR0_VREFCA
D13_DDR0_VREFDQ
D13_DDR1_VREFCA
D13_DDR1_VREFDQ
VDDC15_D13_DDR
VDDC15_D13_DDR
C12104
0.1uF
C12105
0.1uF
C12106
0.1uF
C12107
0.1uF
D13_DDR1_VREFDQ
VDDC15_D13_DDR
D13_DDR1_VREFCA
VDDC15_D13_DDR
D13_DDR0_VREFDQ
VDDC15_D13_DDR
D13_DDR0_VREFCA
VDDC15_D13_DDR
H5TQ2G63DFR-PBC
IC12100
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ2G63DFR-PBC
IC12101
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
NC_5
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
IC12000
LG1153
HEVC
DDR_A[0]
T11
DDR_A[1]
T13
DDR_A[2]
T9
DDR_A[3]
T7
DDR_A[4]
U16
DDR_A[5]
U8
DDR_A[6]
U15
DDR_A[7]
T8
DDR_A[8]
T15
DDR_A[9]
T10
DDR_A[10]
U17
DDR_A[11]
U14
DDR_A[12]
U13
DDR_A[13]
U10
DDR_A[14]
T14
DDR_A[15]
T12
DDR_BA[0]
U7
DDR_BA[1]
T16
DDR_BA[2]
U11
DDR_U_CK
V15
DDR_U_CK_N
W15
DDR_D_CK
V6
DDR_D_CK_N
W6
DDR_CKE
U12
DDR_ODT
T5
DDR_RAS_N
U5
DDR_CAS_N
U6
DDR_WE_N
T6
DDR_RST_N
U9
DDR_ZQ_CALIB
T17
DDR_DQS[0]
W5
DDR_DQS_N[0]
V5
DDR_DQS[1]
W7
DDR_DQS_N[1]
Y7
DDR_DQS[2]
W14
DDR_DQS_N[2]
V14
DDR_DQS[3]
W16
DDR_DQS_N[3]
Y16
DDR_DM[0]
Y8
DDR_DM[1]
Y5
DDR_DM[2]
Y17
DDR_DM[3]
Y14
DDR_DQ[0]
W3
DDR_DQ[1]
W10
DDR_DQ[2]
V2
DDR_DQ[3]
V9
DDR_DQ[4]
Y2
DDR_DQ[5]
Y10
DDR_DQ[6]
W2
DDR_DQ[7]
V10
DDR_DQ[8]
W9
DDR_DQ[9]
W4
DDR_DQ[10]
V8
DDR_DQ[11]
V3
DDR_DQ[12]
V7
DDR_DQ[13]
Y4
DDR_DQ[14]
W8
DDR_DQ[15]
V4
DDR_DQ[16]
W12
DDR_DQ[17]
V18
DDR_DQ[18]
V11
DDR_DQ[19]
W19
DDR_DQ[20]
Y11
DDR_DQ[21]
Y19
DDR_DQ[22]
W11
DDR_DQ[23]
V19
DDR_DQ[24]
W18
DDR_DQ[25]
W13
DDR_DQ[26]
V17
DDR_DQ[27]
V12
DDR_DQ[28]
V16
DDR_DQ[29]
Y13
DDR_DQ[30]
W17
DDR_DQ[31]
V13
HEVC option sheet
THERMAL
THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
10uF
C12203
VREF_D13_M0
VDD33_D13
L12208
BLM18PG121SN1D
R12208
1K
1%
VDDC15_D13_DDR
VDDC15_D13_DDR
C12252
0.1uF
+3.3V_NORMAL
L12206
BLM18PG121SN1D
VREF_D13_M1
VDDC15_D13_DDR
C12249
0.1uF
C12242
0.1uF
4.7uF
C12246
10uF
C12237
+2.5V_Normal
C12259
0.1uF
OPT
4.7uF
C12245
R12210
1K
1%
10uF
C12200
C12244
0.1uF
C12204
0.1uF
+3.3V_NORMAL
4.7uF
C12257
C12253
0.1uF
OPT
VDD25_D13_XTAL
VDD25_D13
+2.5V_Normal
VDD33_D13_XTAL
R12207
1K
1%
C12247
0.1uF
R12209
1K
1%
VDDC11_D13_XTAL
C12239
0.1uF
C12240
0.1uF
C12205
0.1uF
L12210
BLM18PG121SN1D
10uF
C12250
10uF
C12243
L12207
BLM18PG121SN1D
L12209
BLM18PG121SN1D
C12248
0.1uF
C12260
0.1uF
C12251
0.1uF
10uF
C12238
22uF
C12241
+1.1V_D13_VDD
L12211
BLM18PG121SN1D
C12232
22uF
10V
10V
R12205
10K
C12229
22uF
10V
C12218
3300pF
50V
3300pF
50V
C12214
1uF
10V
1uF
10V
IC12201
TPS54327DDAR
3
VREG5
2
VFB
4
SS
1
EN
5
GND
6
SW
7
VBST
8
VIN
9
[EP]GND
L12201
BLM18PG121SN1D
C12208
100pF
50V
C12225
0.1uF
16V
C12202
10uF
16V
10uF
16V
+1.1V_D13_VDD
C12231
22uF
10V
10V
R12206
10K
C12227
22uF
10V
C12216
3300pF
50V
3300pF
50V
C12213
1uF
10V
1uF
10V
IC12200
TPS54327DDAR
3
VREG5
2
VFB
4
SS
1
EN
5
GND
6
SW
7
VBST
8
VIN
9
[EP]GND
L12200
BLM18PG121SN1D
C12207
100pF
50V
C12224
0.1uF
16V
C12201
10uF
16V
10uF
16V
L12204
3.6uH
SM-8040
+1.5V_D13_DDR
R12202
3.6K
1%
R12200
18K
1%
R12203
22K
1%
R12201
15K
1%
R12204
33K
1%
L12205
2.2uH
NR5040T2R2N
VDDC11_D13_XTAL
VDDC15_D13_DDR
VDD25_D13
VDD25_D13_XTAL
VDD33_D13
VDD33_D13_XTAL
VREF_D13_M0
VREF_D13_M1
+1.5V_D13_DDR
+12V
+12V
+1.1V_D13_VDD
+1.1V_D13_VDD
ZD12200
2.5V
OPT
ZD12201
2.5V
OPT
IC12000
LG1153
HEVC
DVDD11_1
H8
DVDD11_2
H9
DVDD11_3
H10
DVDD11_4
H11
DVDD11_5
H12
DVDD11_6
H13
DVDD11_7
J8
DVDD11_8
J13
DVDD11_9
M8
DVDD11_10
K13
DVDD11_11
L13
DVDD11_12
M9
DVDD11_13
M10
DVDD11_14
M11
DVDD11_15
M12
DVDD11_16
M13
DVDD11_XTAL
T1
AVDD11_HDMI_1
L8
AVDD11_HDMI_2
K8
AVDD11_PLL
T2
DVDD15_DDR_1
P5
DVDD15_DDR_2
P6
DVDD15_DDR_3
P7
DVDD15_DDR_4
P8
DVDD15_DDR_5
P9
DVDD15_DDR_6
P10
DVDD15_DDR_7
P11
DVDD15_DDR_8
P12
DVDD15_DDR_9
P13
DVDD15_DDR_10
P14
DVDD15_DDR_11
P15
DVDD15_DDR_12
P16
DVDD15_DDR_13
P17
DVDD25_OTP
J6
AVDD25_HDMI_1
K6
AVDD25_HDMI_2
L6
AVDD25_PLL
U2
DVDD33_1
E10
DVDD33_2
E11
DVDD33_3
E12
DVDD33_4
G6
DVDD33_5
J15
DVDD33_6
K15
DVDD33_7
L15
DVDD33_XTAL
U1
VREF0_DDR
W1
VREF1_DDR
W20
VSS_1
A2
VSS_2
A3
VSS_3
A8
VSS_4
A15
VSS_5
A19
VSS_6
B8
VSS_7
B15
VSS_8
B18
VSS_9
B19
VSS_10
B20
VSS_11
C4
VSS_12
C5
VSS_13
C6
VSS_14
C7
VSS_15
C8
VSS_16
C9
VSS_17
C10
VSS_18
C11
VSS_19
C12
VSS_20
C13
VSS_21
C14
VSS_22
C15
VSS_23
C16
VSS_24
C17
VSS_25
C18
VSS_26
D4
VSS_27
D5
VSS_28
D6
VSS_29
D7
VSS_30
D8
VSS_31
D9
VSS_32
D10
VSS_33
D11
VSS_34
D12
VSS_35
D13
VSS_36
D14
VSS_37
D15
VSS_38
D16
VSS_39
D17
VSS_40
D18
VSS_41
E4
VSS_42
E5
VSS_43
E6
VSS_44
E7
VSS_45
E8
VSS_46
E9
VSS_47
E13
VSS_48
E14
VSS_49
E15
VSS_50
E16
VSS_51
E17
VSS_52
E18
VSS_53
E19
VSS_54
E20
VSS_55
F3
VSS_56
F4
VSS_57
F17
VSS_58
F18
VSS_59
F19
VSS_60
F20
VSS_61
G3
VSS_62
G4
VSS_63
G7
VSS_64
G8
VSS_65
G9
VSS_66
G10
VSS_67
G11
VSS_68
G12
VSS_69
G13
VSS_70
G14
VSS_71
G15
VSS_72
G17
VSS_73
G18
VSS_74
H3
VSS_75
H4
VSS_76
H6
VSS_77
H7
VSS_78
H14
VSS_79
H15
VSS_80
H17
VSS_81
H18
VSS_82
J3
VSS_83
J4
VSS_84
J7
VSS_85
J9
VSS_86
J10
VSS_87
J11
VSS_88
J12
VSS_89
J14
VSS_90
J17
VSS_91
J18
VSS_92
K3
VSS_93
K4
VSS_94
K7
VSS_95
K9
VSS_96
K10
VSS_97
K11
VSS_98
K12
VSS_99
K14
VSS_100
K17
VSS_101
K18
VSS_102
L3
VSS_103
L4
VSS_104
L7
VSS_105
L9
VSS_106
L10
VSS_107
L11
VSS_108
L12
VSS_109
L14
VSS_110
L17
VSS_111
L18
VSS_112
M3
VSS_113
M4
VSS_114
M6
VSS_115
M7
VSS_116
M14
VSS_117
M15
VSS_118
M17
VSS_119
M18
VSS_120
N3
VSS_121
N4
VSS_122
N17
VSS_123
N18
VSS_124
N19
VSS_125
N20
VSS_126
P1
VSS_127
P2
VSS_128
P3
VSS_129
P4
VSS_130
P18
VSS_131
P19
VSS_132
P20
VSS_133
R3
VSS_134
R4
VSS_135
R5
VSS_136
R6
VSS_137
R7
VSS_138
R8
VSS_139
R9
VSS_140
R10
VSS_141
R11
VSS_142
R12
VSS_143
R13
VSS_144
R14
VSS_145
R15
VSS_146
R16
VSS_147
R17
VSS_148
R18
VSS_149
R19
VSS_150
R20
VSS_151
T3
VSS_152
T4
VSS_153
T18
VSS_154
T19
VSS_155
T20
VSS_156
U3
VSS_157
U4
VSS_158
U18
VSS_159
U19
VSS_160
U20
VSS_161
V1
VSS_162
V20
+1.1V_D13_VDD
Switching freq: 700K
R1
3A
R2
Vout=0.765*(1+R1/R2)= 1.113V
+1.5V_D13_DDR
Switching freq: 700K
R1
3A
R2
Vout=0.765*(1+R1/R2)=1.516V
HEVC option sheet
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