DOWNLOAD LG 65LA9650-CA (CHASSIS:LC34N) Service Manual ↓ Size: 7.26 MB | Pages: 55 in PDF or view online for FREE

Model
65LA9650-CA (CHASSIS:LC34N)
Pages
55
Size
7.26 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
65la9650-ca-chassis-lc34n.pdf
Date

LG 65LA9650-CA (CHASSIS:LC34N) Service Manual ▷ View online

THERMAL
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
A_GND
C6905
10uF
25V
LNB
R6900
2.2K
1W
LNB
A_GND
L6900
15uH
SP-7850_15
LNB
R6904
0
I2C_SDA4
C6907
10uF
25V
LNB
R6901
33
LNB
D6901
30V
MBR230LSFT1G
LNB
C6910
0.1uF
50V
LNB
C6911
0.22uF
LNB
+12V
D6900
LNB
LNB_OUT
D6903-*1
40V
LNB_SX34
D6902
30V
LNB
C6903
0.01uF
50V
LNB
R6902
33
LNB
C6906
10uF
25V
LNB
A_GND
D6904-*1
40V
LNB_SX34
A_GND
A_GND
R6903
39K
1/16W
1%
LNB
A_GND
D6903
40V
LNB_SMAB34
D6904
40V
LNB_SMAB34
LNB_TX
C6904
0.1uF
50V
LNB
C6908
0.1uF
LNB
C6909
10uF
25V
LNB
C6912
0.1uF
LNB
C6902
0.22uF
25V
LNB
I2C_SCL4
C6900
18pF
LNB
C6901
33pF
LNB
IC6900
A8303SESTR-T 
LNB
1
VCP
3
NC_1
7
SCL
9
ADD
10
TONECTRL
11
TCAP
12
ISET
13
VREG
14
GND
15
VIN
16
LX
17
GNDLX
18
NC_2
19
NC_3
20
BOOST
5
TDO
8
SDA
6
IRQ
4
TDI
2
LNB
21
[EP]GND
69
LNB
2012.03.08
Input trace widths should be sized to conduct at least 3A
Ouput trace widths should be sized to conduct at least 2A
DVB-S2 LNB Part Allegro
Surge protectioin
close to VIN pin(#15)
Max 1.3A
close to Boost pin(#1)
(Option:LNB)
2A
3.5A
Close to Tuner
Caution!! need isolated GND 
3A
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
TXBCLKP/TX2P
R7217
0
UD
TXC3N
TXB0N/TX5N
TXC2P
TXB3N/TX1N
TXBCLKN/TX2N
BPL_IN
C7201
10uF
16V
OPT
R7208
0
OLED
TXA0N/TX11N
TXC0P
I2C_SDA1
TXC0N
TXA0P/TX11P
R7214
10K
LVDS_BIT_SEL_LOW
TXC2N
R7204
0
OLED
TXA4P/TX6P
TXCCLKP
L7201
120-ohm
LVDS
R7215
10K
OLED
TXACLKP/TX8P
TXB4N/TX0N
TXA1P/TX10P
R7209
0
OLED
TXB3P/TX1P
TXB2P/TX3P
P7202
FI-RE41S-HF-J-R1500 
LVDS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
TXC4N
TXC4P
TXC1P
TXA4N/TX6N
TXC3P
T_CON_SYS_POWER_OFF
TXA2N/TX9N
TXACLKN/TX8N
TXB0P/TX5P
R7216
0
OLED
TXA2P/TX9P
TXA3P/TX7P
TXCCLKN
TXC1N
T_CON_SYS_POWER_OFF
P7201
FI-RE51S-HF-J-R1500 
LVDS
1
NC
2
NC
3
NC
4
NC
5
NC
6
NC
7
LVDS_SEL
8
NC
9
NC
10
L/DIM_ENABLE
11
GND
12
RA0N
13
RA0P
14
RA1N
15
RA1P
16
RA2N
17
RA2P
18
GND
19
RACLKN
20
RACLKP
21
GND
22
RA3N
23
RA3P
24
RA4N
25
RA4P
26
GND
27
BIT_SEL
28
RB0N
29
RB0P
30
RB1N
31
RB1P
32
RB2N
33
RB2P
34
GND
35
RBCLKN
36
RBCLKP
37
GND
38
RB3N
39
RB3P
40
RB4N
41
RB4P
42
GND
43
GND
44
GND
45
GND
46
GND
47
NC
48
VLCD
49
VLCD
50
VLCD
51
VLCD
52
GND
PA168_RESET
TXA3N/TX7N
R7213
0
ALEF
TXB1N/TX4N
TXB1P/TX4P
TXB4P/TX0P
I2C_SCL1
LED_R
C7203
0.1uF
16V
LVDS
TXB2N/TX3N
FRC_FLASH_WP
INV_CTL
PANEL_VCC
TXA1N/TX10N
TXA1N
TXB2P
TXA4P
TXB2N
TXB1P
TXACLKN
TXA1P
TXB0P
TXB1N
TXA4N
TXACLKP
TXB0N
R7201 0
UD_CPBOX
I2C_SCL1
R7200 0
UD_CPBOX
I2C_SDA1
URSA7_RESET
FRC_DONE
R7202
0
UD
R7203
0
UD
R7205
0
UD
LVDS INTERFACE
[41Pin LVDS OUTPUT Connector] 
[51Pin LVDS OUTPUT Connector] 
BIT_SEL
LVDS
TXD3N/TX13N
TXD2P/TX15P
TXD0N/TX17N
TXD1P/TX16P
TXD2N/TX15N
TXD3P/TX13P
TXD4P/TX12P
TXDCLKN/TX14N
TXD4N/TX12N
TXD1N/TX16N
TXDCLKP/TX14P
TXD0P/TX17P
H13 BALL NAME
BSD-NC4_H072-HD
2012-10-15
OLED : FRC_RESET = LVDS_VAL
       INV_CTL = ELVDD_ON
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
D13_SPI_DO_M
D13_SPI_SCLK_M
D13_SPI_DI_M
D13_HDMI_TX0N
D13_HDMI_TX0P
D13_HDMI_TX1N
D13_HDMI_TX1P
D13_HDMI_TXCN
D13_HDMI_TXCP
D13_HDMI_TX2N
D13_HDMI_TX2P
D13_STPO_CLK
D13_STPO_SOP
D13_STPO_VAL
D13_STPO_ERR
D13_STPO_DATA
XTAL_OUT
XTAL_IN
R12007
1M
XTAL_OUT
XTAL_IN
SPI_DL_MODE
+3.3V_NORMAL
3.3K
R12016
D13_TDO_1
D13_TDI_1
P12000
12507WS-08L
1
2
3
4
5
6
7
8
9
+3.3V_NORMAL
D13_TRST_N_1
C12001
0.1uF
16V
R12004
33
R12003
33
R12002
33
R12000
33
R12001
33
D13_TCK_1
D13_TMS_1
D13_UART_RX_1
D13_UART_TX_1
P12001
12507WS-04L
1
2
3
4
5
+3.3V_NORMAL
R12006
33
R12005
33
C12002
0.1uF
16V
D13_SPI_CS/GPIO[0]
R12018
10K
OPT
R12015
0
1/16W
5%
D13_SPI_DO_M
D13_SPI_DI_M
C12005
0.1uF
D13_FLASH_WP
D13_SPI_SCLK_M
R12032
3.3K
R12017
10K
IC12001
MX25L3206EM2I-12G
3
WP#
2
SO/SIO1
4
GND
1
CS#
5
SI/SIO0
6
SCLK
7
HOLD#
8
VCC
R12019
33
+3.3V_NORMAL
D13_SPI_CS/GPIO[0]
R12010
10K
+3.3V_NORMAL
R12011
10K
OPT
D13_UART_RX_1
D13_UART_RX_0
D13_UART_TX_1
D13_UART_TX_0
D13_TMS_1
D13_TCK_0
D13_TCK_1
D13_TMS_0
D13_TDI_0
D13_TDI_1
D13_TRST_N_0
D13_TDO_0
D13_TRST_N_1
D13_TDO_1
R12027
33
R12026
33
R12025
33
SOC_SPI0_MOSI
SOC_SPI0_MISO
D13_TMS_0
D13_TDI_0
D13_TCK_0
D13_TRST_N_0
D13_TDO_0
D13_UART_TX_0
D13_UART_RX_0
R12037
1.6K 1%
D13_HDMI_DDC_DA
D13_HDMI_HPD
D13_HDMI_DDC_CK
R12024
33
SOC_SPI0_SCLK
SOC_SPI0_CS0
R12028
33
R12030
33
I2C_SCL2
R12029
33
R12031
33
I2C_SDA2
D13_SPI_CS/GPIO[0]
C12004
0.01uF
D13_FLASH_WP
I2C_SDA2
D13_SPI_SCLK_M
R12046
0
+3.3V_NORMAL
R12039
0
I2C_SCL2
R12043
1K
R12038
0
D13_SPI_DI_M
R12042
0
P12002
12507WS-10L
1
2
3
4
5
6
7
8
9
10
11
R12044
0
OPT
R12040
0
R12047
0
R12041
0
SPI_DL_MODE
R12045
0
OPT
D13_SPI_CS/GPIO[0]
D13_SPI_DO_M
IC12000
LG1132-D13
IC_D13
XTALI
R2
XTALO
R1
PORES_N
A18
TRST_N0
E1
TMS0
C3
TCK0
D1
TDI0
B1
TDO0
D3
TRST_N1
E2
TMS1
B3
TCK1
D2
TDI1
B2
TDO1
C2
UART_RXD0
B10
UART_TXD0
A10
UART_RXD1
B9
UART_TXD1
A9
SPI_SCLK_S
C20
SPI_CS_S
D20
SPI_DO_S
D19
SPI_DI_S
C19
SPI_SCLK_M
A14
SPI_CS_M
B14
SPI_DO_M
B13
SPI_DI_M
A13
SCL_S
A11
SDA_S
B11
SCL_M
A12
SDA_M
B12
STPI_CLK
G20
STPI_SOP
H19
STPI_VAL
G19
STPI_ERR
H20
STPI_DATA[0]
J19
STPI_DATA[1]
J20
STPI_DATA[2]
K19
STPI_DATA[3]
K20
STPI_DATA[4]
L19
STPI_DATA[5]
L20
STPI_DATA[6]
M19
STPI_DATA[7]
M20
GPIO[7]
B7
GPIO[6]
A7
GPIO[5]
B6
GPIO[4]
A6
GPIO[3]
B5
GPIO[2]
A5
GPIO[1]
B4
GPIO[0]
A4
HDMI_DDC_CK
G1
HDMI_DDC_DA
G2
HDMI_HPD
J2
HDMI_REXT
J1
HDMI_CEC
H2
HDMI_DDCCEC
H1
HDMI_TX0N
M1
HDMI_TX0P
M2
HDMI_TX1N
L1
HDMI_TX1P
L2
HDMI_TX2N
K1
HDMI_TX2P
K2
HDMI_TXCN
N1
HDMI_TXCP
N2
SMODE[0]
F2
SMODE[1]
E3
TMODE[0]
A16
TMODE[1]
B16
TMODE[2]
A17
TMODE[3]
B17
D13_FLASH_WP
+3.3V_NORMAL
R12055
3.3K
X12000
24.75MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
C12003
27pF
50V
C12000
27pF
50V
D13_RESET
R12008
33
R12012
33
R12022
33
R12023
33
R12033
33
C12261
10pF
R12014
33
D13_SMODE[0]
D13_SMODE[1]
R12013
10K
+3.3V_NORMAL
R12021
10K
R12009
10K
OPT
D13_SMODE[1]
+3.3V_NORMAL
D13_SMODE[0]
R12020
10K
OPT
+3.3V_NORMAL
R12034
3.3K
R12035
3.3K
R12036
3.3K
OPT
R12048
3.3K
OPT
D13_INT
R12049
10
XTAL(24.75MHz)
JTAG for HEVC
UART For HEVC
Write Protection
- HIGH : Normal Operation
- LOW : Write Protection
SPI FLASH(4MByte)
GPIO[0] 
- 1 : Serial Flash Boot
- 0 : Live Boot
Closed to D13
Serial Flash Boot Test
HEVC option sheet
SMODE[1:0] 
- 00 : Normal Mode
- Other : Test Mode
H/W Option : default low
SPI Clock Frq. &
Number of applied DDR
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