DOWNLOAD LG 55SL80YR-MA (CHASSIS:LP91T) Service Manual ↓ Size: 4.33 MB | Pages: 27 in PDF or view online for FREE

Model
55SL80YR-MA (CHASSIS:LP91T)
Pages
27
Size
4.33 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
55sl80yr-ma-chassis-lp91t.pdf
Date
PREV: LG 55SL80YR-LA / 55SL80YR-TA (CHASSIS:LP91T) Service Manual

LG 55SL80YR-MA (CHASSIS:LP91T) Service Manual ▷ View online

THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
URSA_D0P
MEMC_DQSB2
100
R1146
URSA_D1M
URSA_C4M
0.1uF
C1123
MEMC_MCLKZ
URSA_A2M
+1.8V_MEMC
0
R1130
READY
URSA_D3M
0
READY
R1132
MEMC_RXO4+
10uF
16
V
C1150
4.7K
READY
R1129
URSA_C3P
OPC_EN
URSA_C0M
MEMC_MCLK1
M_SPI_CK
URSA_D1M
OPC_OUT2
URSA_D4M
120-ohm
L1103
120-ohm
L1105
OPC_OUT1
URSA_A3P
E-DIM
0.01uF
C1133
MEMC_RXEC+
URSA_B3P
MEMC_DQM0
URSA_B4P
0.1uF
C1134
URSA_D2P
URSA_DCKM
URSA_A0M
URSA_C1P
820
R1110
10uF
C1140
URSA_C2P
URSA_B1M
URSA_B1M
URSA_D4P
+3.3V_MEMC
M_XTALI
1M
R1124
M_SPI_CK
MEMC_DQM3
URSA_CCKP
MEMC_RXE2-
MEMC_DQM2
URSA_D3P
URSA_B2P
0.1uF
C1143
MEMC_DQSB1
MEMC_RXO2+
M_SPI_DO
MEMC_DQS2
0.1uF
C1107
M_XTALO
+3.3V_MEMC
0.1uF
C1152
MEMC_DQS3
URSA_B2M
MEMC_DQSB3
URSA_D1P
MEMC_RXE4-
URSA_C0P
M_SDA
MEMC_DQM1
0.1uF
C1119
BLM18PG121SN1D
L1106
MEMC_DQ[0-15]
ISP_RXD_TR
URSA_B0P
56
R1121
URSA_B3M
100
R1153
URSA_D3P
0
R1109
100
R1154
MEMC_RXE1-
0.1uF
C1101
0.1uF
C1142
100
R1157
URSA_A1P
URSA_BCKM
100
R1152
URSA_A4P
MEMC_RXO1-
M_SPI_DI
100
R1155
MEMC_RXO0+
URSA_B1P
URSA_C3P
100
R1156
URSA_A4M
MEMC_DQ[16-31]
56
R1125
1K
READY
R1115
22uF
16V
C1115
URSA_C2P
URSA_B3M
0.1uF
C1136
URSA_C1M
URSA_DCKP
URSA_BCKP
+3.3V_MEMC
22uF
C1139
LVDS_SEL
+3.3V_MEMC
MEMC_RXOC-
+1.26V_MEMC
URSA_C3M
+3.3V_MEMC
MEMC_RXE3+
120-ohm
L1104
URSA_D2M
URSA_C0P
URSA_ACKM
URSA_A3M
URSA_D0M
10K
R1104
10K
R1103
ISP_RXD_TR
MEMC_RXO3+
10uF
10
V
C1126
MEMC_RXE1+
URSA_BCKM
URSA_D2M
0.1uF
C1109
1K
READY
R1102
URSA_A2P
0.1uF
C1149
URSA_C2M
URSA_B2P
URSA_B1P
URSA_A1M
URSA_D2P
1uF
C1103
10uF
C1116
0.1uF
C1130
1K
R1101
+3.3V_MEMC
URSA_D4P
URSA_A0P
URSA_C4P
URSA_ACKP
LED_DEMO
0.1uF
C1110
MEMC_RXE0-
0.1uF
C1137
0.1uF
C1124
URSA_CCKM
ISP_TXD_TR
0.1uF
C1105
URSA_C4M
0.1uF
C1108
URSA_C4P
0.1uF
C1144
0.1uF
C1114
URSA_B0M
120-ohm
L1101
0.1uF
C1122
URSA_A4P
AFLC_EN
15pF
C1147
MEMC_ODT
URSA_A0P
URSA_B0M
LED_DEMO
URSA_B3P
MEMC_RXOC+
LVDS_SEL
1K
R1116
MEMC_MCLK
0.1uF
C1113
URSA_A1P
URSA_C0M
MEMC_RASZ
URSA_C1P
URSA_B0P
0.1uF
C1141
MEMC_RXE3-
15pF
C1148
MEMC_WEZ
0.1uF
C1125
MEMC_RXO3-
MEMC_RXE4+
120-ohm
L1102
MEMC_RXO4-
MEMC_DQSB0
0.1uF
C1102
MEMC_BA1
AFLC_EN
0.1uF
C1128
URSA_D0P
1K
READY
R1117
URSA_D0M
ISP_TXD_TR
MEMC_RXE2+
URSA_C3M
URSA_BCKP
10uF
C1121
M_SPI_CZ
0.1uF
C1138
URSA_C2M
10K
R1122
URSA_A3M
MEMC_DQS0
1K
R1114
MEMC_CASZ
M_SPI_CZ
+3.3V_MEMC
MEMC_MCLKE
MEMC_RXO1+
URSA_B4M
URSA_ACKM
URSA_D1P
URSA_A2M
0.1uF
C1131
56
R1120
0.1uF
C1129
URSA_A4M
URSA_A3P
URSA_D4M
10K
R1111
W25X20AVSNIG
IC1101
IC1101_URSA_winbond
3
WP
2
DO
4
GND
1
CS
5 DIO
6 CLK
7 HOLD
8 VCC
+12V_LCD
MEMC_A[0-12]
10uF
C1117
0.1uF
C1145
MEMC_BA0
MEMC_DQS1
56
R1126
M_SPI_DI
M_SCL
M_XTALI
0.1uF
C1132
0.1uF
C1118
10uF
10V
C1120
URSA_ACKP
URSA_A2P
0.1uF
C1111
1uF
C1135
0.1uF
C1112
URSA_A1M
MEMC_RESET
MEMC_RXO0-
URSA_CCKP
12MHz
X1101
URSA_B2M
10uF
C1127
0.1uF
C1106
URSA_B4M
MEMC_MCLKZ1
MEMC_RXE0+
22uF
16V
C1104
URSA_A0M
0.1uF
C1146
+3.3V_MEMC
URSA_DCKM
URSA_B4P
MEMC_RXO2-
URSA_DCKP
+3.3V_MEMC
100
R1151
M_SPI_DO
+3.3V_MEMC
100
R1150
MEMC_RXEC-
M_XTALO
100
R1149
URSA_C1M
100
R1148
1000pF
C1151
URSA_CCKM
URSA_D3M
100
R1147
0 READY
R1141
0
R1113
VESA
0
R1145
READY
0 READY
R1143
0 READY
R1140
0
R1119
READY
0
R1136
READY
0
READY
R1144
0 READY
R1137
0 READY
R1142
22
R1138
22
OPC_EN
R1128
22
R1123
READY
22
R1139
4.7K
READY
R1134
4.7K
READY
R1133
4.7K
READY
R1135
4.7K
R1112
JEIDA
4.7K
READYR1131
4.7K
READY
R1118
470
R1127
[ E 1 ]
[ D 1 ]
[ L 9 ]
[ N 5 ]
[ N 4 ]
[ N 1 2 ]
[ N 1 3 ]
LGE7329A
IC1100
E1 SDAS
D1 SCLS
F1 GPIO[8]
G1 GPIO[9]
K8 GND_14
E5 VDDC_1
E2 GPIO[10]
F2 GPIO[11]
F3 GPIO[12]
G2 GPIO[13]
M4 GPIO[22]
M5 GPIO[23]
G3 GPIO[14]
E4 GPIO[15]
F4 GPIO[16]
G4 GPIO[17]
H4 GPIO[18]
J4 GPIO[19]
K4 GPIO[20]
L4 GPIO[21]
J6 VDDP_2
H9 GND_7
F6 VDDC_2
H1 MDATA[20]
H2 MDATA[19]
H3 MDATA[17]
J1 MDATA[22]
J2 MDATA[27]
J3 MDATA[28]
K1 MDATA[25]
K2 MDATA[30]
K6 AVDD_DDR_2
K3 DQM[3]
L1 DQM[2]
J8 GND_10
L2 DQS[2]
L3 DQSB[2]
L6 AVDD_DDR_4
L8 VDDP_3
H10 GND_8
M1 DQS[3]
M2 DQSB[3]
L7 AVDD_DDR_5
M3 MDATA[31]
N1 MDATA[24]
J9 GND_11
N2 MDATA[26]
N3 MDATA[29]
L10 AVDD_DDR_6
P1 MDATA[23]
R1 MDATA[16]
T1 MDATA[18]
T2 MDATA[21]
R2 MCLK[0]
P2 MCLKZ[0]
G7 GND_1
L9 AVDD_MEMPLL
N5 MVREF
N4 ODT
T3
RASZ
R3
CASZ
P3
MADR[0]
T4
MADR[2]
R4
MADR[4]
J10
GND_12
P4
MADR[6]
T5
MADR[8]
R5
MADR[11]
P5
WEZ
T6
BADR[1]
R6
BADR[0]
P6
MADR[1]
T7
MADR[10]
L11
AVDD_DDR_7
R7
MADR[5]
P7
MADR[9]
T8
MADR[12]
R8
MADR[7]
P8
MADR[3]
N8
MCLKE
K10
GND_16
F7
VDDC_3
T9
MDATA[4]
R9
MDATA[3]
K7
GND_13
P9
MDATA[1]
T10
MDATA[6]
K11
AVDD_DDR_3
R10
MDATA[11]
P10
MDATA[12]
T11
MDATA[9]
R11
MDATA[14]
J11
AVDD_DDR_1
P11
DQM[1]
T12
DQM[0]
R12
DQS[0]
P12
DQSB[0]
H11
VDDP_1
T13
DQS[1]
R13
DQSB[1]
P13
MDATA[15]
T14
MDATA[8]
R14
MDATA[10]
P14
MDATA[13]
T15
MDATA[7]
R15
MDATA[0]
P15
MDATA[2]
T16
MDATA[5]
R16
MCLK[1]
P16
MCLKZ[1]
N9
GPIO[26]
N10
GPIO[27]
N11
GND_17
M11
RESET
G6
VDDC_4
N12
GPIO[28]
N13
GPIO[29]
N14
GPIO[30]
L13
SCK
M13
SDI
M12
SDO
K13
CSZ
L12
PWM1
K12
PWM0
J13
GPIO[0]
H13
GPIO[1]
G13
GPIO[2]
F13
GPIO[3]
E13
GPIO[4]
F12
GPIO[5]
D14
GPIO[6]
E12
GPIO[7]
N6
GPIO[24]
H6
VDDC_5
N15
LVD4M
N16
LVD4P
M14
LVD3M
M15
LVD3P
F8
AVDD_33_1
M16
LVDCKM
L16
LVDCKP
L15
LVD2M
L14
LVD2P
G9
GND_3
K14
LVD1M
J14
LVD1P
J16
LVD0M
J15
LVD0P
H15
LVC4M
H16
LVC4P
H14
LVC3M
G14
LVC3P
G16
LVCCKM
G15
LVCCKP
F15
LVC2M
F16
LVC2P
F14
LVC1M
E14
LVC1P
E16
LVC0M
E15
LVC0P
G10
GND_4
F9
AVDD_33_2
D16
LVB4M
D15
LVB4P
C16
LVB3M
B16
LVB3P
A16
LVBCKM
A15
LVBCKP
B15
LVB2M
C15
LVB2P
D2
GPIO_3
E3
GPIO_10
E10
GPIO_11
D10
GPIO_7
D8
GPIO_5
D12
REXT
C14
LVB1M
C13
LVB1P
A13
LVB0M
B13
LVB0P
D7
GPIO_4
D9
GPIO_6
B12
LVA4M
A12
LVA4P
C12
LVA3M
C11
LVA3P
A11
LVACKM
B11
LVACKP
B10
LVA2M
A10
LVA2P
C10
LVA1M
C9
LVA1P
A9
LVA0M
B9
LVA0P
F10
AVDD_PLL
G8
GND_2
D11
GPIO_8
D13
GPIO_9
E11
GPIO_12
N7
GPIO[25]
D6
SCLM
D5
SDAM
A14
GPIO_1
B14
GPIO_2
D3
XIN
D4
XOUT
K16
GPIO_14
K15
GPIO_13
H7
GND_5
G11
AVDD_LVDS_2
B8
RO0N
A8
RO0P
C8
RO1N
C7
RO1P
A7
RO2N
B7
RO2P
B6
ROCKN
A6
ROCKP
C6
RO3N
C5
RO3P
A5
RO4N
B5
RO4P
H8
GND_6
F11
AVDD_LVDS_1
B4
RE0N
A4
RE0P
C4
RE1N
C3
RE1P
A3
RE2N
B3
RE2P
B2
RECKN
A2
RECKP
C2
RE3N
C1
RE3P
A1
RE4N
B1
RE4P
GND_9J7
GND_15
K9
0
R1106
0
R1105
100
R1107
100
R1108
CIC21J501NE
L1107
TF05-51S
P1101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
TF05-41S
P1102
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
1K
READY
R1159
1K
R1160
1K
READY
R1100
1K
R1158
+3.3V_MEMC
0 READY
R1161
RT1C3904-T112
Q1101
E
B
C
+3.3V_MULTI_MST
JP1100
JP1102
JP1101
0
READY R1162
MX25L2005MC-12G 
IC1101-*1
IC1101_URSA_Replace_macronix
3
WP
2
SO
4
GND
1
CS
5
S I
6
SCLK
7
HOLD
8
VCC
SMAW250-04Q
P1103
DEBUG
1
2
3
4
5
MEMC_DQ[25]
MEMC_DQ[8]
MEMC_A[7]
MEMC_DQ[0]
MEMC_DQ[10]
MEMC_DQ[11]
MEMC_DQ[24]
MEMC_DQ[17]
MEMC_DQ[29]
MEMC_DQ[1]
MEMC_DQ[7]
MEMC_DQ[6]
MEMC_DQ[15]
MEMC_DQ[28]
MEMC_DQ[3]
MEMC_DQ[4]
MEMC_DQ[30]
MEMC_DQ[31]
MEMC_A[2]
MVREF
MEMC_A[4]
MEMC_A[12]
MEMC_DQ[9]
MEMC_A[11]
MEMC_DQ[18]
MEMC_DQ[12]
MEMC_A[10]
MEMC_DQ[5]
MEMC_A[0]
MEMC_DQ[19]
MEMC_DQ[13]
MEMC_DQ[14]
MEMC_A[3]
MEMC_DQ[27]
MEMC_DQ[21]
MEMC_A[1]
MEMC_A[6]
MEMC_DQ[2]
MEMC_DQ[20]
MEMC_DQ[23]
MEMC_DQ[16]
MEMC_A[8]
MEMC_A[9]
MEMC_DQ[26]
MEMC_DQ[22]
MEMC_A[5]
EAX61181901
Mstar LCD SL80
1 1     1 2
H6 SL80
2 0 0 9 / 0 4 / 0 2
MEMC & LVDS Out
LOW
HIGH
SPI FLASH
I2C
SPI
HIGH
PWM0
HIGH
LOW
PWM1
EEPROM
HIGH
HIGH
HIGH
C l o s e d   t o   I C 1 1 0 0
HIGH
XTAL
GPIO8
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
MEMC_BA0
0.1uF
C1211
+1.8V_MEMC
22uF
C1247
MEMC_MCLKE
0.1uF
C1213
56
AR1204
0.1uF
C1215
MEMC_DQM0
56
R1216
1K 1%
R1223
0
R1233
0.1uF
C1246
MEMC_BA1
56
R1205
10uF 25V
C1253
0.1uF
C1240
MEMC_DQSB3
0.1uF
C1236
22
AR1205
1000pF
C1239
+1.8V_MEMC_DDR
MEMC_DQ[16-31]
0.1uF
C1230
100uF16V
C1251
MEMC_BA1
MEMC_BA0
A_URSA_WEZ
MEMC_MCLKZ
22
AR1206
0.1uF
C1209
56
AR1202
0.1uF
C1225
MEMC_DQ[0-15]
56
R1219
BD9130EFJ-E2
IC1203
3
ITH
2
VCC
4
GND
1
ADJ
5
PGND
6
SW
7
PVCC
8
EN
+1.8V_MEMC_DDR
MEMC_MCLKZ1
+1.8V_MEMC_DDR
0.1uF
C1250
0.1uF
C1207
150
READY
R1201
BLM18PG121SN1D
L1201
B_URSA_WEZ
MEMC_DQS1
+1.8V_MEMC
22
AR1207
MEMC_MCLKE
0.1uF
C1261
B_URSA_MCLKE
B_URSA_WEZ
56
R1210
10K
R1227
10K 1%
R1231
22
R1213
A_URSA_BA1
MEMC_A[0-12]
A_URSA_CASZ
0.1uF
C1232
A_URSA_BA1
P_12V
22
R1202
22
AR1210
17.4K 1%
R1232
B_URSA_BA1
39K
R1236
18nF 16V
C1259
MEMC_DQSB1
0.1uF
C1252
30K 1%
R1229
+1.8V_MEMC
DDRA_A[0-12]
MEMC_CASZ
0.1uF
C1218
0.1uF
C1241
0.1uF
C1229
0.1uF
C1206
MEMC_CASZ
56
R1209
330pF
C1245
B_URSA_BA0
0.1uF
C1238
0.1uF
C1210
BLM18PG121SN1D
L1202
22
AR1211
10uF 25V
C1254
56
AR1214
56
AR1203
A_URSA_BA0
MEMC_RASZ
22
AR1209
0.1uF
C1262
100uF
C1243
12K
R1237
0.1uF
16
V
C1221
A_URSA_CASZ
0.1uF
C1231
0.1uF
C1214
10uF 16V
C1257
MEMC_DQS2
0.1uF
C1234
56
R1215
150READY
R1220
MEMC_ODT
A_URSA_RASZ
DDR_DQ[0-15]
22
R1212
MEMC_MCLK1
0.1uF
C1220
0.1uF
C1267
A_URSA_BA0
0.1uF
C1235
22
AR1217
56
R1208
MEMC_DQM1
0.1uF
C1217
0.1uF
C1226
10uF
10
V
C1202
22
R1211
10uF
C1227
+1.8V_MEMC
+1.8V_MEMC_DDR
B_URSA_CASZ
22
AR1218
MEMC_DQSB2
0.1uF
C1208
A_URSA_MCLKE
10uF 16V
C1258
MEMC_RASZ
56
AR1216
B_URSA_RASZ
MEMC_WEZ
10uF
C1222
B_URSA_CASZ
0.1uF
C1223
MEMC_DQM3
MP2212DN
IC1205
3 IN
2 GND
4 BS
1 FB
5
VCC
6
SW_1
7
SW_2
8
EN/SYNC
0.1uF
C1228
0.1uF
C1216
MEMC_DQM2
A_URSA_MCLKE
56
AR1201
0.1uF
C1219
22
AR1208
18K
R1225
10
R1234
0.1uF
C1201
B_URSA_BA1
1uF
C1264
10uF 16V
C1260
DDR_DQ[0-15]
A_URSA_RASZ
0.1uF
C1224
+3.3V_MEMC
39K 1%
R1228
22uF
C1244
10uF
C1212
1K
R1230
A_URSA_WEZ
1K 1%
R1222
+1.8V_MEMC_DDR
22
AR1212
+1.8V_MEMC_DDR
22
R1204
10K
R1235
+1.8V_MEMC_DDR
0.1uF
C1204
B_URSA_MCLKE
MEMC_DQS3
DDR_DQ[16-31]
56
R1207
+1.8V_MEMC_DDR
DDRB_A[0-12]
10uF
C1203
0.1uF
C1237
DDRB_A[0-12]
22
R1203
+1.26V_MEMC
10uF 10V
C1249
1000pF
C1242
DDR_DQ[16-31]
56
R1217
56
AR1215
56
R1218
B_URSA_RASZ
0.1uF
C1233
0.1uF
C1248
56
AR1213
MEMC_DQSB0
56
R1206
1K 1%
R1221
56
R1214
MEMC_DQS0
MEMC_ODT
1K 1%
R1224
MEMC_MCLK
MEMC_WEZ
1uF 25V
C1255
B_URSA_BA0
+3.3V_MEMC
0.1uF
C1205
DDRA_A[0-12]
3.6uH
L1204
APE8953MP
IC1204
3
VOUT_1
2
FB
4
VOUT_2
1
GND
5 VIN
6 VCNTL
7 POK
8 EN
500
L1206
500
L1205
2.2uH
L1203
+5V_MULTI
+5V_MULTI
HYB18TC512160CF-2.5
IC1202
QIMONDA
J 2
VREF
J 8
CK
H2 VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8 VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J 7
VSSDL
L7
CAS
F2 VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J 1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8 VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7 VSSQ5
D8 VSSQ6
D2 VSSQ7
A7 VSSQ8
B8 VSSQ9
B2 VSSQ10
P9 VSS1
N1 VSS2
J 3 VSS3
E3 VSS4
A3 VSS5
G9 VDDQ1
G7 VDDQ2
G3 VDDQ3
G1 VDDQ4
E9 VDDQ5
C9 VDDQ6
C7 VDDQ7
C3 VDDQ8
C1 VDDQ9
A9 VDDQ10
R1 VDD1
M9 VDD2
J 9 VDD3
E1 VDD4
A1 VDD5
B9 DQ15
B1 DQ14
D9 DQ13
D1 DQ12
D3 DQ11
D7 DQ10
C2 DQ9
C8 DQ8
F9 DQ7
F1 DQ6
H9 DQ5
H1 DQ4
H3 DQ3
H7 DQ2
G2 DQ1
G8 DQ0
HYB18TC512160CF-2.5
IC1201
QIMONDA
J 2 VREF
J 8 CK
H2
VSSQ2
B7 UDQS
N8 A4
P8 A8
L1 NC4
L2 BA0
R8 NC3
K7 RAS
F8
VSSQ3
F3 LDM
P3 A9
M3 A1
N3 A5
K8 CK
R3 NC5
L3 BA1
J 7 VSSDL
L7 CAS
F2
VSSQ4
B3 UDM
M2 A10/AP
K2 CKE
R7 NC6
M7 A2
N7 A6
M8 A0
J 1 VDDL
K3 WE
E8 LDQS
P7 A11
K9 ODT
A2 NC1
N2 A3
P2 A7
H8
VSSQ1
F7 LDQS
A8 UDQS
R2 A12
L8 CS
E2 NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J 3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J 9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
0
R1226
0.47uF
C1256
H5PS5162FFR-S6C
Hynix
I C 1 2 0 1 - * 1
J 2
VREF
J 8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J 7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J 1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J 3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J 9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
H5PS5162FFR-S6C
Hynix
I C 1 2 0 2 - * 1
J 2
VREF
J 8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J 7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J 1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J 3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J 9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
EDE5116AJBG-8E-E
IC1201-*2
ELPIDA
J 2
VREF
J 8
CK
H2
VSSQ_2
B7
UDQS
N8
A4
P8
A8
L1
NC_4
L2
BA0
R8
NC_3
K7
RAS
F8
VSSQ_3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC_5
L3
BA1
J 7
VSSDL
L7
CAS
F2
VSSQ_4
B3
UDM
M2
A10
K2
CKE
R7
NC_6
M7
A2
N7
A6
M8
A0
J 1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC_1
N2
A3
P2
A7
H8
VSSQ_1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC_2
E7
VSSQ_5
D8
VSSQ_6
D2
VSSQ_7
A7
VSSQ_8
B8
VSSQ_9
B2
VSSQ_10
P9
VSS_1
N1
VSS_2
J 3
VSS_3
E3
VSS_4
A3
VSS_5
G9
VDDQ_1
G7
VDDQ_2
G3
VDDQ_3
G1
VDDQ_4
E9
VDDQ_5
C9
VDDQ_6
C7
VDDQ_7
C3
VDDQ_8
C1
VDDQ_9
A9
VDDQ_10
R1
VDD_1
M9
VDD_2
J 9
VDD_3
E1
VDD_4
A1
VDD_5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
EDE5116AJBG-8E-E
ELPIDA
IC1202-*2
J 2
VREF
J 8
CK
H2
VSSQ_2
B7
UDQS
N8
A4
P8
A8
L1
NC_4
L2
BA0
R8
NC_3
K7
RAS
F8
VSSQ_3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC_5
L3
BA1
J 7
VSSDL
L7
CAS
F2
VSSQ_4
B3
UDM
M2
A10
K2
CKE
R7
NC_6
M7
A2
N7
A6
M8
A0
J 1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC_1
N2
A3
P2
A7
H8
VSSQ_1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC_2
E7
VSSQ_5
D8
VSSQ_6
D2
VSSQ_7
A7
VSSQ_8
B8
VSSQ_9
B2
VSSQ_10
P9
VSS_1
N1
VSS_2
J 3
VSS_3
E3
VSS_4
A3
VSS_5
G9
VDDQ_1
G7
VDDQ_2
G3
VDDQ_3
G1
VDDQ_4
E9
VDDQ_5
C9
VDDQ_6
C7
VDDQ_7
C3
VDDQ_8
C1
VDDQ_9
A9
VDDQ_10
R1
VDD_1
M9
VDD_2
J 9
VDD_3
E1
VDD_4
A1
VDD_5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
100pF
READY
C1200
DDR_DQ[24]
MEMC_A[2]
DDR_DQ[28]
DDR_DQ[5]
DDRB_A[7]
DDR_DQ[9]
MEMC_DQ[21]
DDRA_A[4]
DDRB_A[6]
MEMC_A[11]
DDR_DQ[31]
MEMC_A[1]
DDRA_A[6]
DDRB_A[8]
MEMC_DQ[25]
DDR_DQ[13]
MEMC_DQ[12]
DDRA_A[1]
MEMC_A[7]
DDR_DQ[20]
MEMC_DQ[23]
DDRA_A[3]
MEMC_A[11]
MEMC_DQ[30]
MEMC_DQ[24]
MEMC_A[12]
DDRA_A[12]
DDRA_A[11]
DDR_DQ[10]
MEMC_A[4]
MEMC_DQ[6]
DDR_DQ[21]
DDRB_A[0]
MEMC_DQ[22]
MEMC_A[10]
MEMC_DQ[5]
DDRA_A[7]
DDRB_A[9]
DDRA_A[12]
DDR_DQ[26]
MEMC_A[6]
DDRB_A[5]
DDRA_A[9]
DDRA_A[2]
DDR_DQ[26]
DDRB_A[11]
DDR_DQ[9]
MEMC_A[1]
DDR_DQ[8]
DDR_DQ[2]
MEMC_DQ[19]
MEMC_A[3]
MEMC_DQ[18]
MEMC_DQ[16]
DDRA_A[8]
MEMC_DQ[26]
DDR_DQ[23]
MEMC_A[7]
DDR_DQ[21]
DDR_DQ[28]
DDR_DQ[12]
DDR_DQ[30]
DDR_DQ[7]
MEMC_A[8]
MEMC_DQ[0]
DDR_DQ[30]
DDRB_A[4]
MEMC_A[0]
DDRA_A[9]
DDR_DQ[25]
DDR_DQ[20]
DDR_DQ[17]
MEMC_DQ[14]
DDR_DQ[14]
MEMC_A[12]
DDRB_A[5]
DDR_DQ[25]
DDR_DQ[7]
MEMC_A[4]
DDR_DQ[1]
MEMC_A[9]
DDRA_A[10]
DDR_DQ[27]
DDR_DQ[8]
DDR_DQ[29]
MEMC_DQ[3]
DDRB_A[12]
DDRA_A[1]
DDR_DQ[3]
DDR_DQ[27]
MEMC_DQ[15]
MEMC_A[10]
MEMC_DQ[4]
MEMC_A[2]
DDR_DQ[2]
MEMC_DQ[11]
MEMC_DQ[29]
DDR_DQ[4]
DDR_DQ[17]
DDRB_A[4]
MEMC_A[5]
DDRA_A[4]
DDR_DQ[29]
DDRA_A[0]
DDRB_A[6]
DDR_DQ[22]
DDR_DQ[19]
DDR_DQ[15]
DDR_DQ[11]
MEMC_DQ[8]
DDR_DQ[15]
DDR_DQ[16]
DDR_DQ[5]
DDR_DQ[22]
DDRB_A[1]
DDRA_A[11]
MEMC_A[3]
DDR_DQ[23]
DDRA_A[3]
DDRA_A[6]
DDR_DQ[24]
MEMC_A[5]
DDR_DQ[10]
MEMC_DQ[13]
DDR_DQ[11]
MEMC_A[0]
DDRB_A[11]
DDR_DQ[1]
DDRB_A[12]
DDRB_A[3]
DDR_DQ[0]
MEMC_DQ[1]
MEMC_DQ[9]
MEMC_DQ[27]
MEMC_DQ[17]
DDRB_A[7]
MEMC_DQ[28]
MEMC_DQ[20]
DDR_DQ[14]
DDRA_A[5]
DDRB_A[2]
DDR_DQ[18]
MEMC_A[6]
DDR_DQ[4]
DDRB_A[3]
DDRA_A[2]
DDR_DQ[6]
DDRB_A[2]
DDRB_A[8]
MEMC_DQ[7]
DDRA_A[0]
MEMC_DQ[10]
MEMC_DQ[31]
MEMC_DQ[2]
DDRB_A[10]
DDRB_A[0]
MEMC_A[9]
DDRA_A[7]
DDR_DQ[18]
DDR_DQ[31]
DDR_DQ[16]
DDRB_A[9]
DDRA_A[5]
DDR_DQ[3]
DDRB_A[1]
DDR_DQ[12]
DDR_DQ[19]
DDRA_A[10]
MEMC_A[8]
DDR_DQ[6]
DDRB_A[10]
DDR_DQ[0]
DDR_DQ[13]
DDRA_A[8]
EAX61181901
Mstar LCD SL80
H6 SL80
1 2     1 2
MEMC_DDR & POWER
2 0 0 9 / 0 4 / 0 2
R2
Vo=0.8(1+R1/R2)
V0 = 0.8(1+R1/R2)
R2
1000 mA @85% efficiency
233 mA+400mA+600mA
2A
V0 = 0.8(1+R1/R2)
DDR2 1.8V By CAP - Place these Caps near Memory
+1.8V_MEMC for DDR
R1
R1
+1.26V Core for MEMC
MAX 3A
600 mA
400mA + 600mA
+3.3V_MEMC
MAX 2A
R1
R2
1300 mA @85% efficiency
DDR2 1.8V By CAP - Place these Caps near Memory
Close to IC1204
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