DOWNLOAD LG 55LX6500-CA (CHASSIS:LC03R) Service Manual ↓ Size: 9.01 MB | Pages: 48 in PDF or view online for FREE

Model
55LX6500-CA (CHASSIS:LC03R)
Pages
48
Size
9.01 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
55lx6500-ca-chassis-lc03r.pdf
Date
PREV: LG 55LX950N-ZA (CHASSIS:LD03R) Service Manual

LG 55LX6500-CA (CHASSIS:LC03R) Service Manual ▷ View online

THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
LVRX2_CLKM001:AG35
LVRX2_BP
001:AG34
LVRX1_EM
001:E33
LVRX2_BM
001:AG34
LVRX2_AP
001:AG35
LVRX1_CP
001:E34
LVRX2_EP
001:AG33
LVRX2_DP
001:AG34
LVRX2_CM
001:AG34
LVRX1_DP
001:E34
LVRX1_EP
001:E33
LVRX1_AM
001:E35
LVRX1_CLKP
001:E35
LVRX2_CP
001:AG34
LVRX1_DM
001:E33
LVRX2_DM
001:AG33
LVRX1_BM
001:E34
LVRX2_EM
001:AG33
LVRX2_AM
001:AG35
LVRX1_BP
001:E34
FRC_RESET
001:I17
LVRX1_CM
001:E34
LVRX2_CLKP001:AG35
LVRX1_CLKM
001:E35
LVRX1_AP
001:E35
VSYNC
001:AD17
R812
0
OPT
R802
0
R803
0
OPT
3D_SYNC_OUT
009:AK20
R801
0
R804
0
FPGA_VSYNC
010:AX10
L801
120-ohm
VLCD_POWER
ZD800
5.5V
OPT
TVS
I2C_SCL
VDD_LCM
(+16V)
ZD801
5.5V
OPT
TVS
I2C_SDA
C805
10uF
25V
C806
10uF
25V
P802
FI-R51S-HF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I2C_SCL
001:E19;005:AA16;008:F18;008:AL4;009:AP8
I2C_SDA
001:E19;005:AA15;008:N18;008:AL4;009:AP11
IC801
BUF16821AIPWPR
3
OUT2
2
OUT1
4
OUT3
1
VCOM2
6
OUT5
5
OUT4
7
OUT6
8
GNDA_1
9
VS_1
10
OUT7
11
OUT8
12
OUT9
13
VSD
14
SCL
15
SDA
16
AO
17
BKSEL
18
GNDD
19
OUT10
20
OUT11
21
OUT12
22
OUT13
23
VS_2
24
GNDA_2
25
OUT14
26
OUT15
27
OUT16
28
VCOM1
R822
0
V13
008:AE19;008:AL15
V14
008:AE19;008:AL15
L800
120-ohm
I2C_SCL
001:E19;005:AA16;008:V24;008:AL4;009:AP8
R833
0
R810
0
V5
008:AE20;008:AL16
R808
33
C825
OPT
V3
008:AE21;008:AL17
V18
008:AE18;008:AL14
R831
0
R830
0
V4
008:AE21;008:AL17
R832
0
R824
0
V1
008:AE21;008:AL17
R827
0
V10
008:AE20;008:AL16
V7
008:AE20;008:AL16
V2
008:AE21;008:AL17
V6
008:AE20;008:AL16
R823
0
C802
0.1uF
50V
VDD_LCM
(+16V)
I2C_SDA
001:E19;005:AA15;008:V25;008:AL4;009:AP11
R825
0
R806
0
R807
0
R826
0
VCC_LCM
(+3.3V)
P_VCOM 006:H14
R829
0
R809
0
R828
0
R811
33
C824
OPT
V16
008:AE19;008:AL15
V12
008:AE19;008:AL15
R805
0
V9
008:AE20;008:AL16
V17
008:AE18;008:AL14
C801
0.1uF
50V
V15
008:AE19;008:AL15
R821
33
V17
008:N24;008:AL14
RRMV5P
004:V22
GSP
004:AD15;008:AL18
RRMV2P
004:V20
C817
0.01uF
50V
VCC_LCM
(+3.3V)
P805
104060-8017
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
RLMV6N
004:V18
RRMV2N
004:V20
RRMV6N
004:V23
LRMVCLKN
005:T20
V1
008:F24;008:AL17
RRMV4N
004:V22
POL
004:AI17;008:AE18
V13
008:N21;008:AE19
V15
008:N22;008:AE19
V2
008:F24;008:AL17
VCOMLOUT
006:D13
V4
008:F23;008:AE21
V9
008:F20;008:AL16
V15
008:N22;008:AL15
VCC_LCM
(+3.3V)
C818
0.1uF
50V
RLMVCLKN
004:V17
VGL
(-5V)
LLMV0P
005:T14
SOE_R
004:AI13
SOE_L
004:AD13
HVDD
(+8V)
RLMV1P
004:V15
GSC 004:AN17;008:AE23
VCOMLFB
006:H16
V6
008:F22;008:AL16
V10
008:F19;008:AL16
RRMV0P
004:V19
V4
008:F23;008:AL17
LLMV1N
005:T14
RLMV1N
004:V15
RRMV1P
004:V19
RRMVCLKN
004:V21
LLMV2N
005:T15
LLMV2P
005:T15
V5
008:F22;008:AL16
C816
0.1uF
50V
LRMV5N
005:T21
OPT_P
004:R10
LLMV5N
005:T17
RLMV6P
004:V18
H_CONV
004:O10;008:AL18
H_CONV
004:O10;008:AE17
LRMV0N
005:T18
OPT_N
004:R10;008:AL19
RRMV6P
004:V22
V7
008:F20;008:AL16
V7
008:F20;008:AE20
LRMV6N
005:T22
V14
008:N21;008:AL15
RRMV4P
004:V21
RLMVCLKP
004:V16
LRMV2P
005:T19
LRMV4P
005:T21
V16
008:N23;008:AL15
LRMV4N
005:T21
VDD_LCM
(+16V)
V12
008:N20;008:AL15
RRMV0N
004:V19
RRMVCLKP
004:V21
RLMV0P
004:V14
LLMV4P
005:T16
V1
008:F24;008:AE21
V16
008:N23;008:AE19
VCOMRFB
006:H17
V14
008:N21;008:AE19
V12
008:N20;008:AE19
GOE 004:AC17;008:AE23
GSP
004:AD15;008:AE18
VGL
(-5V)
GOE
004:AC17;008:AL12
C820
0.01uF
50V
VDD_LCM
(+16V)
LRMVCLKP
005:T20
V6
008:F22;008:AE20
OPT_N
004:R10;008:AE17
POL
004:AI17;008:AL18
V10
008:F19;008:AE20
RLMV2P
004:V15
Z_OUT
008:AL14
VGH
(+24V)
LRMV6P
005:T22
LRMV2N
005:T19
LLMV6N
005:T17
VGH
(+24V)
V2
008:F24;008:AE21
LLMVCLKP
005:T16
RLMV2N
004:V16
HVDD
(+8V)
LRMV1P
005:T19
GSC
004:AN17;008:AL12
LLMV6P
005:T17
LLMV1P
005:T14
RLMV5N
004:V18
LRMV5P
005:T21
RLMV5P
004:V17
V3
008:F23;008:AE21
LRMV1N
005:T19
LLMV5P
005:T17
C819
0.1uF
50V
LRMV0P
005:T18
Z_OUT
008:AE22
P806
104060-8017
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
V3
008:F23;008:AL17
RLMV0N
004:V14
VCOMROUT
006:H18
V17
008:N24;008:AE18
LLMVCLKN
005:T16
RRMV5N
004:V22
V5
008:F22;008:AE20
V18
008:N24;008:AE18
RLMV4N
004:V17
RRMV1N
004:V20
LLMV4N
005:T16
LLMV0N
005:T14
V13
008:N21;008:AL15
V18
008:N24;008:AL14
C814
0.1uF
50V
V9
008:F20;008:AE20
RLMV4P
004:V17
C810
10uF
25V
C815
10uF
25V
C804
10uF
25V
C803
10uF
25V
C808
10uF
25V
C807
10uF
25V
C809
10uF
25V
C821
10uF
25V
GAMMA_BKSEL
001:AD16
R834
0
OPT
R835
1K
1%
L/R_SYNC
R813
0
R839
0
2V5
Q804
FDV301N
G
D
S
R816
2K
R837
4.7K
Q802
FDV301N
G
D
S
R842
4.7K
R819
0
R845
5.6K
OPT
R841
2K
+3.3V
Q801
FDV301N
G
D
S
R817
4.7K
2V5
R836
2K
R846
2K
E_TMS
R844
0
R818
22
OPT
2V5
E_TDI
Q803
FDV301N
G
D
S
+3.3V
C811
18pF
50V
OPT
TCK
E_TDO
R847
4.7K
R815
5.6K
OPT
+3.3V
R814
0
R840
5.6K
OPT
2V5
E_TCK
R820
5.6K
OPT
+3.3V
P807
12505WR-04A00
OPT
1
2
3
4
5
P804
12507WR-06L
1
2
3
4
5
6
7
P803
12507WR-04L
1
2
3
4
5
E_TMS
VLCD_POWER
E_TCK
E_TDO
E_TDI
L802
120-ohm
3D_DIMMING
010:AY5
3D_DIMMING_2
010:BE5
TCK_FLASH
R849
22
TDO
R838
22
OPT
TDO_FLASH
R850
22
C812
18pF
50V
OPT
R843
22
OPTC813
18pF
50V
OPT
TMS
TMS_FLASH
R851
22
C822
18pF
50V
OPT
R852
22
R848
22
OPT
TDI_FLASH
TDI
1
3D + 240 FRC + TCON BOARD
8
Interface
10
2009. 11. 13
For P-Gamma Data Download
For Shutter Glasses Sync
For LED Sync from 3D Formatter
[LEFT FFC CONNECTOR]
[RIGHT FFC CONNECTOR]
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
/CE
R950
10K
2V5
CONFIG_DONE
R953
1K
OPT
C909
0.1uF
16V
C917
10uF
16V
IC904
EPCS16SI8N_
3
VCC
2
DATA
4
GND
1
NCS
5
ASDI
6
DCLK
7
VCC_1
8
VCC_2
R949
22
R968
22
SYSCLK
R964
22
C920
100pF
50V
X901
54.0000MHz
4
VDD
1
TRISTATE/OPEN
2
GND
3
OUTPUT
C921
10pF
R967
22
2V5
/STATUS
R952
10K
R944
10K
L902
BLM18PG121SN1D
R951
10K
C919
0.1uF
16V
/CONFIG
C903
0.1uF
16V
C901
0.1uF
16V
1V2
2V5
C905
0.1uF
16V
2V5
C907
0.1uF
16V
1V2
2V5
1V2
2V5
1V2
LVTX4_A-
LVTX4_C-
SCL2V5
LVTX4_A+
SDA2V5
LVTX4_CLK-
LVTX4_CLK+
LVTX4_C+
LVTX4_B+
LVTX4_D+
LVTX4_B-
LVTX4_D-
VS_STATUS2V5
MSEL[2]
LVTX1_A+
LVTX1_C+
TA5-
CONFIG_DONE
LVTX1_D+
TB6+
MSEL[0]
2V5
LVTX1_B-
MSEL[1]
TB6-
LVTX1_B+
LVTX1_A-
TCLK5-
LVTX1_D-
TCLK5+
LVTX1_E+
TA5+
1V2
LVTX1_E-
TB5-
LVTX1_C-
SYSCLK
MSEL[3]
TB5+
/RESET2V5
TE6-
TA7-
TB8-
TC8+
TC8-
TD8+
TE8+
TCLK8-
TCLK7-
TCLK8+
TCLK7+
TE6+
TE8-
TD6-
TC6-
TD8-
TA7+
TB7+
TC6+
TCLK6+
2V5
TB7-
TCLK6-
TD6+
TB8+
1V2
MSEL[2]
AR901
22
1/16W
R982
0
OPT
MSEL[0]
MSEL[1]
2V5
R987
0
OPT
R988
0
MSEL[3]
R984
0
OPT
C902
0.1uF
16V
2V5
C904
0.1uF
16V
1V2
C908
0.1uF
16V
C906
0.1uF
16V
2V5
1V2
LVTX5_CLK-
LVTX5_C+
LVTX5_CLK+
LVTX5_B-
LVTX5_A+
LVTX5_C-
LVTX5_B+
LVTX5_A-
TDO
TE2-
/STATUS
TE2+
/CONFIG
ASDO
LVTX8_CLK-
DATA0
LVTX8_CLK+
DCLK
/CSO
TMS
TDI
TCK
/CE
R993
1K
R991
1K
OPT
2V5
R995
22
R996
22
TCK
TDO
R997
22
TMS
TDI
R994
22
R992
1K
C924
0.1uF
16V
R954
1K
OPT
R948
330
OPT
SW901
JTP-1127WEM
OPT
1
2
4
3
C914
0.1uF
16V
OPT
/3D_FPGA_RESET
R958
4.7K
OPT
+3.3V
C911
0.1uF
16V
OPT
IC901
KIA7029AF
OPT
2
G
3
O
1
I
R959
0
OPT
/FPGA_RESET
R963
0
3D_SYNC_OUT
R955
0
R901
100
R903
100
R904
100
R905
100
R937
100
R927
100
R928
100
R930
100
R931
100
R933
100
R938
100
R939
100
R940
100
R941
100
R942
100
LVTX1_CLK-
LVTX1_CLK+
R1901
100
LVTX2_CLK+
LVTX2_CLK-
R1902
100
LVTX3_CLK+
LVTX3_CLK-
R1903
100
LVTX6_CLK+
LVTX6_CLK-
R1904
100
LVTX7_CLK+
LVTX7_CLK-
R1905
100
Q901
2SC3052
E
B
C
+3.3V
R1907
10K
R1906
10K
/3D_FPGA_RESET
R1908
10K
Q902
2SC3052
E
B
C
2V5
R1910
22
/RESET2V5
R916
100
LVTX6_E+
LVTX6_E-
LVTX8_B-
LVTX8_B+
R902
100
R935
100
LVTX5_E-
R907
100
LVTX5_E+
R909
100
LVTX6_A+
LVTX6_A-
LVTX5_D-
R906
100
LVTX5_D+
LVTX8_A-
LVTX8_A+
R932
100
R913
100
LVTX8_D+
LVTX8_D-
LVTX7_C-
R934
100
LVTX7_C+
LVTX6_C-
R911
100
LVTX6_C+
LVTX7_B+
LVTX7_B-
R914
100
LVTX8_C-
LVTX8_C+
R910
100
R917
100
LVTX8_E-
LVTX8_E+
R936
100
LVTX7_D-
LVTX7_D+
LVTX6_D+
LVTX6_D-
R915
100
R912
100
LVTX7_A+
LVTX7_A-
LVTX6_B+
LVTX6_B-
R908
100
R926
100
LVTX2_E+
LVTX2_E-
LVTX3_D+
R918
100
LVTX3_D-
LVTX2_D+
LVTX2_D-
R923
100
R921
100
LVTX2_C-
LVTX2_C+
LVTX2_B+
R922
100
LVTX2_B-
R943
100
LVTX2_A+
LVTX2_A-
R919
100
LVTX3_C+
LVTX3_C-
R929
100
LVTX4_E-
LVTX4_E+
LVTX3_A+
LVTX3_A-
R925
100
LVTX3_B+
LVTX3_B-
R920
100
R924
100
LVTX3_E-
LVTX3_E+
LVTX7_E+
LVTX7_E-
TD2+
TD2-
TD1-
TD1+
TA1-
TA1+
TE3+
TE3-
TE4+
TE4-
TC2+
TC2-
TA2+
TA2-
TE1+
TE1-
TB1+
TB1-
TD3+
TD3-
TD4+
TD4-
TB2-
TB2+
TC1+
TC1-
TCLK2-
TCLK2+
TCLK1+
TCLK1-
TB4+
TB4-
TC4+
TC4-
TC3+
TC3-
TA3-
TA3+
TA4+
TA4-
TB3-
TB3+
TCLK3+
TCLK3-
TCLK4+
TCLK4-
TA6-
TA6+
TE5-
TE5+
TC5-
TC5+
TD5+
TD5-
TE7+
TE7-
TA8+
TA8-
TD7+
TD7-
TC7+
TC7-
2V5
+3.3V
VS_STATUS2V5
R1925
22
OPT
R1921
22
OPT
R1922
5.6K
R1923
2K
R1924
4.7K
OPT
Q905
FDV301N
G
D
S
R1914
5.6K
OPT
Q903
FDV301N
G
D
S
2V5
+3.3V
R1911
22
R1913
2K
I2C_SDA
R1918
2K
R1916
22
2V5
+3.3V
Q904
FDV301N
G
D
S
R1919
5.6K
OPT
I2C_SCL
R1909
4.7K
+3.3V
R1928
22
Q907
2SC3052
E
B
C
R1932
10K
R1931
10K
R1930
10K
Q906
2SC3052
E
B
C
+3.3V
VS_STATUS2V5
FPGA_SDA
FPGA_SCL
SDA2V5
SCL2V5
C910
18pF
50V
OPT
C913
18pF
50V
OPT
R1915
0
R1920
0
R1926
0
OPT
R1927
0
OPT
C915
18pF
50V
OPT
R1929
3.3K
IC1000
EP3C55F484C6N
A11
B8_IO[0]
B11
B8_IO[1]
D10
B8_IO[2]
E10
B8_IO[3]
A10
B8_IO[4]
B10
B8_IO[5]
A9
B8_IO[6]
B9
B8_IO[7]
C10
B8_IO[8]
G11
B8_IO[9]
A8
B8_IO[10]
B8
B8_IO[11]
A7
B8_IO[12]
B7
B8_IO[13]
A6
B8_IO[14]
B6
B8_IO[15]
E9
B8_IO[16]
C8
B8_IO[17]
C7
B8_IO[18]
D8
B8_IO[19]
E8
B8_IO[20]
A5
B8_IO[21]
B5
B8_IO[22]
G10
B8_IO[23]
F10
B8_IO[24]
C6
B8_IO[25]
D7
B8_IO[26]
A4
B8_IO[27]
B4
B8_IO[28]
F8
B8_IO[29]
G8
B8_IO[30]
A3
B8_IO[31]
B3
B8_IO[32]
D6
B8_IO[33]
E7
B8_IO[34]
C3
B8_IO[35]
C4
B8_IO[36]
F7
B8_IO[38]
G7
B8_IO[39]
F9
B8_IO[40]
E6
B8_IO[41]
E5
B8_IO[42]
G9
B8_IO[43]
IC1000
EP3C55F484C6N
F6
VCCD_PLL3
F5
GNDA3
G6
VCCA3
G4
B1_IO[0]
G3
B1_IO[1]
B2
B1_IO[2]
B1
B1_IO[3]
G5
B1_IO[4]
E4
B1_IO[5]
E3
B1_IO[6]
C2
B1_IO[7]
C1
B1_IO[8]
D2
B1_IO[9]
D1
B1_IO[10]
H7
B1_IO[11]
H6
B1_IO[12]
J6
B1_IO[13]
H4
B1_IO[14]
H3
B1_IO[15]
E2
B1_IO[16]
E1
B1_IO[17]
F2
B1_IO[18]
F1
B1_IO[19]
J5
B1_IO[20]
H5
B1_IO[21]
K6
nSTATUS
J7
B1_IO[22]
K7
B1_IO[23]
J4
B1_IO[24]
H2
B1_IO[25]
H1
B1_IO[26]
J3
B1_IO[27]
J2
B1_IO[28]
J1
B1_IO[29]
K2
DCLK
K1
B1_IO[30]
K5
nCONFIG
L5
TDI
L2
TCK
L1
TMS
L4
TDO
L3
nCE
G2
CLK0
G1
CLK1
IC1000
EP3C55F484C6N
T2
CLK2
T1
CLK3
L6
B2_IO[0]
M6
B2_IO[1]
M2
B2_IO[2]
M1
B2_IO[3]
M4
B2_IO[4]
M3
B2_IO[5]
N2
B2_IO[6]
N1
B2_IO[7]
M5
B2_IO[8]
P2
B2_IO[9]
P1
B2_IO[10]
R2
B2_IO[11]
R1
B2_IO[12]
N5
B2_IO[13]
P4
B2_IO[14]
P3
B2_IO[15]
U2
B2_IO[16]
U1
B2_IO[17]
V2
B2_IO[18]
V1
B2_IO[19]
P5
B2_IO[20]
N6
B2_IO[21]
R4
B2_IO[22]
R3
B2_IO[23]
W2
B2_IO[24]
W1
B2_IO[25]
Y2
B2_IO[26]
Y1
B2_IO[27]
T3
B2_IO[28]
N7
B2_IO[29]
P7
B2_IO[30]
AA2
B2_IO[31]
AA1
B2_IO[32]
V4
B2_IO[33]
V3
B2_IO[34]
P6
B2_IO[35]
R5
B2_IO[36]
T4
B2_IO[37]
T5
B2_IO[38]
R6
B2_IO[39]
T6
VCCA1
U5
GNDA1
U6
VCCD_PLL1
IC1000
EP3C55F484C6N
F16
B7_IO[0]
E16
B7_IO[1]
F15
B7_IO[2]
G16
B7_IO[3]
G15
B7_IO[4]
F14
B7_IO[5]
C18
B7_IO[6]
D18
B7_IO[7]
D17
B7_IO[8]
C19
B7_IO[9]
D19
B7_IO[10]
A20
B7_IO[11]
B20
B7_IO[12]
C17
B7_IO[13]
B19
B7_IO[14]
A19
B7_IO[15]
A18
B7_IO[16]
B18
B7_IO[17]
D15
B7_IO[18]
E15
B7_IO[19]
G14
B7_IO[20]
G13
B7_IO[21]
A17
B7_IO[22]
B17
B7_IO[23]
A16
B7_IO[24]
B16
B7_IO[25]
C15
B7_IO[26]
E14
B7_IO[27]
F13
B7_IO[28]
A15
B7_IO[29]
B15
B7_IO[30]
C13
B7_IO[31]
D13
B7_IO[32]
E13
B7_IO[33]
A14
B7_IO[34]
B14
B7_IO[35]
A13
B7_IO[36]
B13
B7_IO[37]
E12
B7_IO[38]
E11
B7_IO[39]
F11
B7_IO[40]
A12
CLK8
B12
CLK9
IC1000
EP3C55F484C6N
G22
CLK5
G21
CLK4
M18
CONF_DONE
M17
MSEL0
L18
MSEL1
L17
MSEL2
K20
MSEL3
L22
B6_IO[0]
L21
B6_IO[1]
K19
B6_IO[2]
K22
B6_IO[3]
K21
B6_IO[4]
J22
B6_IO[5]
J21
B6_IO[6]
H22
B6_IO[7]
H21
B6_IO[8]
K17
B6_IO[9]
K18
B6_IO[10]
J18
B6_IO[11]
F22
B6_IO[12]
F21
B6_IO[13]
J20
B6_IO[14]
J19
B6_IO[15]
J17
B6_IO[16]
H20
B6_IO[17]
H19
B6_IO[18]
E22
B6_IO[19]
E21
B6_IO[20]
H18
B6_IO[21]
H16
B6_IO[22]
D22
B6_IO[23]
D21
B6_IO[24]
F20
B6_IO[25]
F19
B6_IO[26]
G18
B6_IO[27]
H17
B6_IO[28]
C22
B6_IO[29]
C21
B6_IO[30]
B22
B6_IO[31]
B21
B6_IO[32]
C20
B6_IO[33]
D20
B6_IO[34]
F17
B6_IO[35]
G17
B6_IO[36]
F18
VCCA2
E18
GNDA2
E17
VCCD_PLL2
IC1000
EP3C55F484C6N
V17
VCCD_PLL4
V18
GNDA4
U18
VCCA4
AA22
B5_IO[0]
AA21
B5_IO[1]
T17
B5_IO[2]
T18
B5_IO[3]
W20
B5_IO[4]
W19
B5_IO[5]
Y22
B5_IO[6]
Y21
B5_IO[7]
U20
B5_IO[8]
U19
B5_IO[9]
W22
B5_IO[10]
W21
B5_IO[11]
T20
B5_IO[12]
T19
B5_IO[13]
R17
B5_IO[14]
P17
B5_IO[15]
V22
B5_IO[16]
V21
B5_IO[17]
R20
B5_IO[18]
U22
B5_IO[19]
U21
B5_IO[20]
R18
B5_IO[21]
R19
B5_IO[22]
N16
B5_IO[23]
R22
B5_IO[24]
R21
B5_IO[25]
P20
B5_IO[26]
P22
B5_IO[27]
P21
B5_IO[28]
N20
B5_IO[29]
N19
B5_IO[30]
N17
B5_IO[31]
N18
B5_IO[32]
N22
B5_IO[33]
N21
B5_IO[34]
M22
B5_IO[35]
M21
B5_IO[36]
M20
B5_IO[37]
M19
B5_IO[38]
M16
B5_IO[39]
T22
CLK7
T21
CLK6
R965
27
R1912
2K
R1917
2K
TDI_FLASH
/CSO
R946
0
EJTAG_TO_FLASH
R945
0
EJTAG_TO_FLASH
TMS_FLASH
DATA0
R956
0
EJTAG_TO_FLASH
TDO_FLASH
DCLK
ASDO
R947
0
EJTAG_TO_FLASH
TCK_FLASH
P901
12505WR-10
1
2
3
4
5
6
7
8
9
10
11
MDS62110201
GAS1-*1
GAS1_4.5T(8x5)
MDS62110201
GAS2-*1
GAS2_4.5T(8x5)
MDS62110201
GAS3-*1
GAS3_4.5T(8x5)
MDS62110201
GAS4-*1
GAS4_4.5T(8x5)
MDS62110201
GAS7-*1
GAS7_4.5T(8x5)
MDS62110201
GAS5-*1
GAS5_4.5T(8x5)
MDS62110201
GAS8-*1
GAS8_4.5T(8x5)
MDS62110201
GAS6-*1
GAS6_4.5T(8x5)
MDS62110201
GAS11-*1
GAS11_4.5T(8x5)
MDS62110201
GAS9-*1
GAS9_4.5T(8x5)
MDS62110201
GAS12-*1
GAS12_4.5T(8x5)
MDS62110201
GAS10-*1
GAS10_4.5T(8x5)
R2237
4.7K
R2236
10K
R2239
0
/CONFIG
FPGA_D/L_CTRL
Q908
2SC3052
E
B
C
2V5
/CE
R2238
22
MDS62110208
GAS9
GAS9_4.5T(8x6)
MDS62110208
GAS1
GAS1_4.5T(8x6)
MDS62110208
GAS8
GAS8_4.5T(8x6)
MDS62110208
GAS7
GAS7_4.5T(8x6)
MDS62110208
GAS3
GAS3_4.5T(8x6)
MDS62110208
GAS11
GAS11_4.5T(8x6)
MDS62110208
GAS5
GAS5_4.5T(8x6)
MDS62110208
GAS10
GAS10_4.5T(8x6)
MDS62110208
GAS12
GAS12_4.5T(8x6)
MDS62110208
GAS4
GAS4_4.5T(8x6)
MDS62110208
GAS2
GAS2_4.5T(8x6)
MDS62110208
GAS6
GAS6_4.5T(8x6)
MDS62110204
GAS7-*2
GAS7_5.5T(8x6)
MDS62110204
GAS4-*2
GAS4_5.5T(8x6)
MDS62110204
GAS8-*2
GAS8_5.5T(8x6)
MDS62110204
GAS5-*2
GAS5_5.5T(8x6)
MDS62110204
GAS2-*2
GAS2_5.5T(8x6)
MDS62110204
GAS1-*2
GAS1_5.5T(8x6)
MDS62110204
GAS11-*2
GAS11_5.5T(8x6)
MDS62110204
GAS6-*2
GAS6_5.5T(8x6)
MDS62110204
GAS9-*2
GAS9_5.5T(8x6)
MDS62110204
GAS12-*2
GAS12_5.5T(8x6)
MDS62110204
GAS10-*2
GAS10_5.5T(8x6)
MDS62110204
GAS3-*2
GAS3_5.5T(8x6)
2V5
+3.3V
L901
BLM18PG121SN1D
OPT
R986
0
R983
0
R989
0
OPT
R985
0
EP3C55_C6N (FPGA IC)
10
9
3D + 240 FRC + TCON BOARD
2009. 11. 13
IR Emitter Vsync Level Shift (2.5V to 3.3V)
FPGA Reset Level Shifter (3.3V to 2.5V)
FPGA I2C Level Shift (3.3V <-> 2.5V)
FPGA DOWNLOAD CONTROL
SMD Gasket - 4.5T (8x6)
SMD Gasket - 4.5T (8x5)
SMD Gasket - 5.5T (8x6)
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
DDR_DQ[28]
DDR_DQ[17]
DDR_DQ[10]
DDR_DQ[0]
SDDR_DQ[20]
DDR_DQ[2]
SDDR_DQ[26]
SDDR_DQ[17]
DDR_DQ[19]
SDDR_DQ[23]
DDR_DQ[9]
DDR_DQ[16]
DDR_DQ[10]
DDR_DQ[29]
DDR_DQ[11]
SDDR_DQ[21]
DDR_DQ[15-0]
DDR_DQ[12]
DDR_DQ[20]
DDR_DQ[30]
DDR_DQ[0]
DDR_DQ[13]
DDR_DQ[15]
DDR_DQ[14]
DDR_DQ[1]
DDR_DQ[15]
DDR_DQ[2]
SDDR_DQ[15]
DDR_DQ[18]
DDR_A[3]
DDR_DQ[21]
DDR_DQ[3]
DDR_A[2]
DDR_DQ[22]
DDR_A[9]
DDR_DQ[4]
SDDR_DQ[25]
SDDR_DQ[18]
DDR_A[8]
DDR_DQ[5]
DDR_A[11]
SDDR_DQ[7]
DDR_DQ[19]
DDR_DQ[3]
DDR_DQ[20]
DDR_DQ[18]
DDR_A[10]
1V8
1V8
DDR_A[2]
DDR_DQ[9]
SDDR_DQ[28]
SDDR_DQ[3]
DDR_A[12-0]
DDR_DQ[31]
SDDR_DQ[9]
SDDR_DQ[30]
DDR_A[12-0]
SDDR_DQ[11]
SDDR_DQ[31]
DDR_DQ[12]
DDR_DQ[23]
DDR_DQ[27]
SDDR_DQ[13]
DDR_DQ[21]
SDDR_DQ[2]
DDR_DQ[24]
DDR_A[1]
DDR_DQ[25]
DDR_DQ[25]
DDR_DQ[13]
DDR_DQ[26]
SDDR_DQ[5]
DDR_DQ[1]
DDR_DQ[27]
DDR_DQ[7]
SDDR_DQ[14]
SDDR_DQ[0]
DDR_A[5]
DDR_A[9]
DDR_A[5]
DDR_DQ[23]
DDR_A[8]
SDDR_DQ[12]
SDDR_DQ[29]
DDR_DQ[5]
DDR_A[1]
DDR_A[11]
DDR_A[12]
DDR_DQ[28]
DDR_A[4]
SDDR_DQ[8]
SDDR_DQ[6]
DDR_A[10]
DDR_A[4]
SDDR_DQ[16]
DDR_A[7]
DDR_DQ[29]
SDDR_DQ[4]
SDDR_DQ[27]
SDDR_DQ[10]
DDR_DQ[17]
DDR_A[12]
DDR_A[6]
DDR_DQ[6]
DDR_DQ[30]
DDR_DQ[14]
DDR_A[0]
DDR_A[3]
DDR_A[7]
DDR_DQ[11]
SDDR_DQ[19]
DDR_DQ[24]
DDR_A[6]
DDR_DQ[4]
DDR_DQ[31-16]
DDR_DQ[8]
DDR_DQ[6]
SDDR_DQ[1]
SDDR_DQ[22]
DDR_DQ[26]
DDR_A[0]
DDR_DQ[31]
DDR_DQ[7]
DDR_DQ[16]
DDR_DQ[22]
SDDR_DQ[24]
DDR_DQ[8]
SDDR_DQ[6]
SDDR_DQ[1]
SDDR_DQ[5]
SDDR_DQ[0]
SDDR_DQ[14]
SDDR_DQ[11]
SDDR_DQ[9]
SDDR_DQ[7]
SDDR_DQ[8]
SDDR_DQ[13]
SDDR_DQ[15]
SDDR_DQ[4]
SDDR_DQ[3]
SDDR_DQ[2]
SDDR_DQ[10]
SDDR_DQ[12]
SDDR_DQ[25]
SDDR_DQ[22]
SDDR_DQ[16]
SDDR_DQ[30]
SDDR_DQ[19]
SDDR_DQ[26]
SDDR_DQ[21]
SDDR_DQ[29]
SDDR_DQ[31]
SDDR_DQ[23]
SDDR_DQ[27]
SDDR_DQ[18]
SDDR_DQ[28]
SDDR_DQ[20]
SDDR_DQ[24]
SDDR_DQ[17]
C1025
0.1uF
16V
C1001
10uF
16V
C1093
0.1uF
16V
C1035
0.1uF
16V
AR1012
56
C1084
0.1uF
16V
AR1016
56
C1098
0.1uF
16V
C1099
0.1uF
16V
C1055
0.1uF
16V
C1046
0.1uF
16V
C2006
0.1uF
16V
C1026
0.1uF
16V
C1059
0.1uF
16V
C1015
0.1uF
16V
C1086
0.1uF
16V
C1091
0.1uF
16V
DDR_VTT
C2000
0.1uF
16V
DDR_A[9]
C1017
0.1uF
16V
C1083
0.1uF
16V
DDR_A[12]
DDR_A[8]
C1081
0.1uF
16V
C1008
0.1uF
16V
C1095
0.1uF
16V
DDR_VTT
C1029
0.1uF
16V
R1012
56
C1056
0.1uF
16V
DDR_A[12]
C1078
0.1uF
16V
DDR2_CKE
DDR_A[2]
C1092
0.1uF
16V
DDR2_ODT
DDR_A[5]
C1022
0.1uF
16V
C1003
0.1uF
16V
C2013
0.1uF
16V
C1097
0.1uF
16V
DDR_A[1]
C1045
0.1uF
16V
C2011
0.1uF
16V
C1065
0.1uF
16V
C1033
0.1uF
16V
C2016
0.1uF
16V
C2009
0.1uF
16V
C1005
0.1uF
16V
DDR_A[6]
DDR_A[10]
C1085
0.1uF
16V
DDR_BA[0]
C1060
0.1uF
16V
C1023
0.1uF
16V
C2004
0.1uF
16V
DDR_A[11]
C1010
0.1uF
16V
C1064
0.1uF
16V
C1058
0.1uF
16V
C1040
0.1uF
16V
C1012
0.1uF
16V
DDR_A[3]
C1094
0.1uF
16V
C1087
0.1uF
16V
C1043
0.1uF
16V
C1048
0.1uF
16V
C2017
0.1uF
16V
C2003
0.1uF
16V
DDR_VTT
C1014
0.1uF
16V
C1079
0.1uF
16V
C1044
0.1uF
16V
C2014
0.1uF
16V
AR1009
56
AR1010
56
C1061
0.1uF
16V
C1054
0.1uF
16V
C2007
0.1uF
16V
DDR_A[4]
C1090
0.1uF
16V
C1007
0.1uF
16V
C1020
0.1uF
16V
C1049
0.1uF
16V
1V2
C2001
0.1uF
16V
DDR_A[7]
C2008
0.1uF
16V
C2002
0.1uF
16V
DDR_A[0]
C2015
0.1uF
16V
DDR_A[11]
DDR2_CKE
/DDR_RAS
C1072
0.1uF
16V
C1096
0.1uF
16V
/DDR_WE
/DDR_WE
1V8
C1024
0.1uF
16V
C1041
0.1uF
16V
C1073
0.1uF
16V
/DDR_CS
C1013
0.1uF
16V
DDR_A[0]
DDR_A[1]
C1032
0.1uF
16V
R1011
56
C2018
0.1uF
16V
C2012
0.1uF
16V
C1037
0.1uF
16V
C1074
0.1uF
16V
AR1014
56
/DDR_RAS
DDR_BA[0]
C1089
0.1uF
16V
2V5
AR1017
56
/DDR_CAS
C1088
0.1uF
16V
1V2
1V8
AR1018
56
C1077
0.1uF
16V
1V8
DDR_A[7]
C1039
0.1uF
16V
DDR_A[5]
C1075
0.1uF
16V
C1036
0.1uF
16V
DDR_BA[1]
C1018
0.1uF
16V
DDR2_ODT
/DDR_CS
C2005
0.1uF
16V
C1082
0.1uF
16V
/DDR_CAS
DDR_A[6]
C1051
0.1uF
16V
AR1011
56
DDR_A[3]
DDR_A[9]
AR1013
56
DDR_A[10]
DDR_A[8]
C1062
0.1uF
16V
C1063
0.1uF
16V
C1002
0.1uF
16V
C2010
0.1uF
16V
C1016
0.1uF
16V
C1080
0.1uF
16V
DDR_A[4]
AR1015
56
DDR_BA[1]
2V5
C1052
0.1uF
16V
C1057
0.1uF
16V
C1021
0.1uF
16V
DDR_A[2]
C1076
0.1uF
16V
C1038
0.1uF
16V
C1034
0.1uF
16V
C1050
0.1uF
16V
C1053
100pF
50V
C1047
10uF
16V
1V2
C1070
10uF
16V
C1067
100pF
50V
C1071
10uF
16V
C1066
100pF
50V
1V8
2V5
C1068
0.1uF
16V
C1069
0.1uF
16V
2V5
DDR_A[0]
FPGA_VSYNC_1V8
DDR_A[8]
/DDR_CAS
DDR_A[2]
DDR_LDQS[0]
DDR2_CLK
/DDR2_CLK
/DDR_RAS
DDR_LDM[0]
DDR_UDQS[0]
DDR_A[9]
DDR_A[1]
DDR_A[4]
DDR_A[11]
DDR_A[6]
/DDR_CS
DDR_A[5]
DDR2_ODT
C1011
470pF
50V
C1009
0.1uF
16V
DDR_VREF0
DDR_BA[0]
DDR_BA[1]
/DDR_WE
DDR_A[12]
DDR_UDQS[1]
DDR_A[10]
DDR_LDQS[1]
DDR_A[3]
DDR_A[7]
DDR_LDM[1]
DDR2_CKE
DDR_UDM[0]
DDR_UDM[1]
C1027
0.1uF
16V
C1030
470pF
50V
DDR_VREF1
/DDR_CAS
DDR_BA[1]
DDR_UDM[1]
/DDR_CAS
C1019
100pF
50V
IC1002
H5PS5162FFR-S6C
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
1V8
C1042
100pF
50V
C1028
0.1uF
16V
DDR2_CLK
/DDR_CS
DDR_LDM[0]
SDDR_DQ[31-16]
R1002 33
SDDR_DQ[15-0]
R1001
100
DDR_BA[0]
/DDR_RAS
DDR_A[12-0]
DDR_A[12-0]
AR1008
33
R1003 33
DDR_LDQS[1]
C1031
470pF
50V
DDR_LDM[1]
AR1005
33
DDR2_CKE
IC1001
H5PS5162FFR-S6C
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR_BA[1]
1V8
DDR2_ODT
DDR_VREF1
DDR2_CLK
AR1004
33
/DDR_RAS
/DDR_CS
AR1007
33
R1005 1K
DDR_BA[0]
DDR2_CKE
DDR_UDQS[1]
/DDR_WE
/DDR2_CLK
R1007 33
R1009 1K
R1006
100
R1010 1K
/DDR2_CLK
AR1001
33
DDR_LDQS[0]
DDR_UDM[0]
AR1006
33
DDR_UDQS[0]
DDR2_ODT
/DDR_WE
R1008 33
R1004 1K
DDR_VREF0
C1006
470pF
50V
AR1003
33
AR1002
33
C1004
0.1uF
16V
SDDR_DQ[15-0]
SDDR_DQ[31-16]
FRAME_INFO_1V8
Q1002
2SC3052
E
B
C
R1013
10K
R1015
10K
Q1001
2SC3052
E
B
C
R1014
10K
R1017
22
+3.3V
3D_FRAME_INFO
FRAME_INFO_1V8
R1022
22
R1020
10K
R1019
10K
+3.3V
Q1003
2SC3052
E
B
C
Q1004
2SC3052
E
B
C
R1018
10K
FPGA_VSYNC_1V8
FPGA_VSYNC
1V8
+3.3V
R1016
3.3K
R1025
10K
R1027
22
R1023
10K
OPT
1V8
Q1005
2SC3052
E
B
C
Q1006
2SC3052
E
B
C
L/R_SYNC
R1026
3.3K
+3.3V
L/R_SYNC_1V8
R1024
10K
L/R_SYNC_1V8
R1021
1K
IC1000
EP3C55F484C6N
J11
VCCINT[0]
J12
VCCINT[1]
L14
VCCINT[2]
M14
VCCINT[3]
P11
VCCINT[4]
P12
VCCINT[5]
L9
VCCINT[6]
M9
VCCINT[7]
J13
VCCINT[8]
J14
VCCINT[9]
K14
VCCINT[10]
J10
VCCINT[11]
K9
VCCINT[12]
N9
VCCINT[13]
P9
VCCINT[14]
P10
VCCINT[15]
P13
VCCINT[16]
P14
VCCINT[17]
N14
VCCINT[18]
J16
VCCINT[19]
K15
VCCINT[20]
L16
VCCINT[21]
M15
VCCINT[22]
R12
VCCINT[23]
R10
VCCINT[24]
R8
VCCINT[25]
H9
VCCINT[26]
G12
VCCINT[27]
J8
VCCINT[28]
M8
VCCINT[29]
T7
VCCINT[30]
T9
VCCINT[31]
T13
VCCINT[32]
P15
VCCINT[33]
H15
VCCINT[34]
H11
VCCINT[35]
K8
VCCINT[36]
L7
VCCINT[37]
D4
VCCIO1[0]
F4
VCCIO1[1]
K4
VCCIO1[2]
N4
VCCIO2[0]
U4
VCCIO2[1]
W4
VCCIO2[2]
AB2
VCCIO3[0]
W5
VCCIO3[1]
W9
VCCIO3[2]
W11
VCCIO3[3]
AB21
VCCIO4[0]
W12
VCCIO4[1]
W16
VCCIO4[2]
W18
VCCIO4[3]
P18
VCCIO5[0]
V19
VCCIO5[1]
Y19
VCCIO5[2]
E19
VCCIO6[0]
G19
VCCIO6[1]
L19
VCCIO6[2]
A21
VCCIO7[0]
D12
VCCIO7[1]
D14
VCCIO7[2]
D16
VCCIO7[3]
A2
VCCIO8[0]
D5
VCCIO8[1]
D9
VCCIO8[2]
D11
VCCIO8[3]
IC1000
EP3C55F484C6N
L10
GND[0]
L11
GND[1]
M10
GND[2]
M11
GND[3]
L12
GND[4]
L13
GND[5]
M12
GND[6]
M13
GND[7]
N11
GND[8]
K11
GND[9]
N12
GND[10]
K12
GND[11]
K13
GND[12]
N13
GND[13]
N10
GND[14]
K10
GND[15]
J9
GND[16]
F12
GND[17]
H12
GND[18]
H13
GND[19]
J15
GND[20]
K16
GND[21]
L15
GND[22]
N15
GND[23]
R13
GND[24]
R11
GND[25]
R9
GND[26]
P8
GND[27]
H14
GND[28]
H10
GND[29]
H8
GND[30]
N8
GND[31]
R7
GND[32]
T8
GND[33]
T12
GND[34]
P16
GND[35]
L8
GND[36]
M7
GND[37]
A1
GND[38]
C5
GND[39]
C9
GND[40]
C11
GND[41]
C12
GND[42]
C14
GND[43]
C16
GND[44]
A22
GND[45]
E20
GND[46]
G20
GND[47]
L20
GND[48]
P19
GND[49]
V20
GND[50]
Y20
GND[51]
AB22
GND[52]
Y18
GND[53]
Y16
GND[54]
Y12
GND[55]
Y11
GND[56]
Y9
GND[57]
Y5
GND[58]
AB1
GND[59]
N3
GND[60]
U3
GND[61]
W3
GND[62]
D3
GND[63]
F3
GND[64]
K3
GND[65]
IC1000
EP3C55F484C6N
AA12
CLK13
AB12
CLK12
AA13
B4_IO[0]
AB13
B4_IO[1]
AA14
B4_IO[2]
AB14
B4_IO[3]
V12
B4_IO[4]
W13
B4_IO[5]
Y13
B4_IO[6]
AA15
B4_IO[7]
AB15
B4_IO[8]
U12
B4_IO[9]
Y14
B4_IO[10]
Y15
B4_IO[11]
AA16
B4_IO[12]
AB16
B4_IO[13]
V13
B4_IO[14]
W14
B4_IO[15]
U13
B4_IO[16]
V14
B4_IO[17]
U14
B4_IO[18]
U15
B4_IO[19]
V15
B4_IO[20]
W15
B4_IO[21]
T14
B4_IO[22]
T15
B4_IO[23]
AB18
B4_IO[24]
AA17
B4_IO[25]
AB17
B4_IO[26]
AA18
B4_IO[27]
AA19
B4_IO[28]
AB19
B4_IO[29]
W17
B4_IO[30]
Y17
B4_IO[31]
AA20
B4_IO[32]
AB20
B4_IO[33]
V16
B4_IO[34]
U16
B4_IO[35]
U17
B4_IO[36]
T16
B4_IO[37]
R16
B4_IO[38]
R14
B4_IO[39]
R15
B4_IO[40]
IC1000
EP3C55F484C6N
V6
B3_IO[0]
V5
B3_IO[1]
U7
B3_IO[2]
U8
B3_IO[3]
Y4
B3_IO[4]
Y3
B3_IO[5]
Y6
B3_IO[6]
AA3
B3_IO[7]
AB3
B3_IO[8]
W6
B3_IO[9]
V7
B3_IO[10]
AA4
B3_IO[11]
AB4
B3_IO[12]
AA5
B3_IO[13]
AA6
B3_IO[14]
AB6
B3_IO[15]
AB5
B3_IO[16]
W7
B3_IO[17]
Y7
B3_IO[18]
U9
B3_IO[19]
V8
B3_IO[20]
W8
B3_IO[21]
AA7
B3_IO[22]
AB7
B3_IO[23]
Y8
B3_IO[24]
T10
B3_IO[25]
T11
B3_IO[26]
V9
B3_IO[27]
V10
B3_IO[28]
U10
B3_IO[29]
AA8
B3_IO[30]
AB8
B3_IO[31]
AA9
B3_IO[32]
AB9
B3_IO[33]
U11
B3_IO[34]
V11
B3_IO[35]
W10
B3_IO[36]
Y10
B3_IO[37]
AA10
B3_IO[38]
AB10
B3_IO[39]
AA11
CLK15
AB11
CLK14
R1028
10K
L/R_SYNC_FRC_OUT
+3.3V
LVDS_STABLE_1V8
1V8
R1029
10K
OPT
FPGA_D/L_CTRL
Q1008
2SC3052
OPT
E
B
C
R1030
10K
OPT
R1032
3.3K
OPT
Q1007
2SC3052
OPT
E
B
C
R1033
22
OPT
R1031
10K
OPT
LVDS_STABLE_1V8
3D_DIMMING_1V8
+3.3V
3D_DIMMING_1V8
R1034
10K
R1038
22
R1037
1K
R1036
10K
Q1010
2SC3052
E
B
C
+3.3V
R1035
10K
3D_DIMMING
Q1009
2SC3052
E
B
C
R1042
1K
R1043
22
R1039
10K
Q1011
2SC3052
E
B
C
R1040
10K
R1041
10K
3D_DIMMING_2_1V8
+3.3V
+3.3V
3D_DIMMING_2
Q1012
2SC3052
E
B
C
3D_DIMMING_2_1V8
3D + 240 FRC + TCON BOARD
10
DDR2
10
2009. 11. 13
3D Frame Info Level Shift (3.3V to 1.8V)
FPGA V-SYNC Level Shift (1.8V to 3.3V)
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