LG 55LW9500-UA (CHASSIS:LA12D) Service Manual ▷ View online
4
Single & 위성_TUNER/LNB/CI Slot/Scart (구주/중국/브라질, 아주, 중아)
LNB_Allegro
(A8290)
DVB-T/C/S2
CI Slot
Scart
TU_RESET, TU_RESET_SUB
I2C(M)
ATV_OUT
IF_AGC_Main
DIF+-
I2C(S)
LNB_INT
PCM_TS_DATA[P]/CLK,SYNC/VAL
S2_reset
TU_SIF
S/W
DTV_OUT
NLASB3157DFT2G
AG
CI
CI
FE
A
A
INP/N
SC
L
L
/DA0_
3.3V
SCL/DA3_3.3V
TU_CVBS
PCM_MDI[P], MISTRT, MIVAL_ERR, MCLKI
FE_TS_DATA[P]
CLK, Sync,VAL_ERR
RF_SWITCH_CTL, RF_BOOSTER_CTL
LNB_TX
H/NIM
F/NIM
LNB_OUT
<DVB-T/C, ISDB-T>
CI_MDI[P], MISTRT
MIVAL_ERR, MCLKI
11
11
11
FE_TS_DATA[P]
CLK, Sync,VAL_ERR
Main SoC
BCM
35230(B0)
5
Block Diagram ( FE & PCMCIA)
PCMCIA
PCMCIA
Card
FLASH _WP Ctrl
CI Detect
(/ CI_CD1 / /CI_CD2)
PCM_VAL_ERR / PCM_CLK / PCM_DATA_SYN
NAND Flash
PCM_MDI[0:7]
PCM_MIVAL_ERR
PCM_MCLKI
PCM_MISTRT
PCM_MCLKI
PCM_MISTRT
CI_TS_DATA[0-7]
CI_TS_CLK / CI_TS_VAL / CI_TS_SYNC
CI_ADDR[5][6][8][10][14]
PCM_Address[0:7]
NAND_DATA[0:7]
NAND_DATA[0:7]
74LVC245A
Bi-Buffer
CI_DATA[0:7]
NAND_DATA[0:7]
Direction Select : NAND_REb
Ci_EN1
Demod
TS_DATA[P]
TS_VAL_ERR / TS_CLK / TS_DATA_SYN
DVB T/C
ATSC
ISDB-T
Demod
CI Detect
DIF_P/N
74LVC125APW
CI_CE1 /CI_CE2
NAND_REb / NAND_WEb
PCM_OE / PCM_WE
CI_TS_DATA[0:7]
CI_TS_MIVAL_ERR
CI_TS_MCLKI
CI_TS_MISTRT
CI_TS_MCLKI
CI_TS_MISTRT
PCM_DATA[0:7}
/PCM_REG(/REG), PCM_RST
IF_AGC
H/NIM
F/NIM
74AHC08PW
/CI_EN1
NAND_REb / NAND_CLE /
NAND_REb / NAND_CLE /
PCM_IORD / PCM_IOWR
PCM_CE1
CI_ADDR[0] / CI_ADDR[1]
5V_CI_ON
74LVC245A
Bi-Buffer
PCM_ADDR[2][3][4][7][9][11][12][13]
CI_ADDR[2][3][4][7][9][11][12][13]
/CI_EN1
BCM35230
(B0)
Main SoC
6
PCMCIA Signal Path
CI_TS_VAL / CI_TS_CLK / CI_TS_SYNC
NAND_DATA[0:7]
NAND FLASH
PCM_MCLKI
PCM_MISTRT
PCM_MIVAL_ERR
PCM_MISTRT
PCM_MIVAL_ERR
DTMB / DVB T/C & T2
F/NIM Tuner
CI_DATA[0:7]
CI slot
Descr
a
m
b
ler
F/NIM
DTMB / DVB-T/C & T2
PCMC
IA
M
ic
o
m
CI_DOUT_DATA [7:0]
CI_TS_DATA[7:0]
74LVC245A
Bi-Buffer
TS_VAL_ERR / TS_CLK / TS_DATA_SYN
TS_DATA[S]
TS_DATA[S]
/PCM_REG(/REG), PCM_RST
74LVC125APW
CI_CE1 /CI_CE2
NAND_REb / NAND_WEb
PCM_OE / PCM_WE
74AHC08PW
/CI_EN1
NAND_REb / NAND_CLE /
PCM_IORD / PCM_IOWR
PCM_CE1
CI_ADDR[1] / CI_ADDR[2]
5V_CI_ON
74LVC245A
Bi-Buffer
CI_ADDR[5][6][8][10][14]
/CI_EN1
PCM_ADDR[2][3][4][7][9]
[11][12][13]
[11][12][13]
PCM_ADDR[2][3][4][7][9]
[11][12][13]
[11][12][13]
BCM35230
(B0)
7
Scart CVBS
Scart R,G,B
Scart ID
Jack Interface
TUNER
Level
generated by TR
0V, 6V,12V
REC_8 Ctrl1
Recording Ctrl
REC_8 Ctrl2
CVBS Out
[ATV_OUT]
Audio L/R out
OPAMP
IC1501
LM324D
Audio L/R In
RGB Control I/O
CVBS in
[I2SSCK_OUTD/GPIO]
[VI_SC_R1],[VI_SC_G1],[VI_SC_B1]
[VI_CVBS1]
[I2SWS_OUTD/GPIO]
[VDAC1]
[ADAC_CL_P/N]
[FS_IN1]
[SC_CVBS_IN]
[SC_FB]
[COMP1_DET]
[COMP1_Y]
[COMP1_Pb]
[COMP1_Pr]
[SC/COMP2_L/R_IN]
Switching IC
NLASB3157DFT2G
DSUB_R / G / B
PC L,R
EDID EEPROM
AT24C02BN-10SU-1.8
RGB DET
[DSUB_R+/G+/B+]
DSUB_ V / HSYNC
[DSUB_V/H SYNC]
[DSUB_DET] // GPIO
[EDID_WP]
MICOM
[RGB_DDC_SCL]
[RGB_DDC_SDA]
RGB_DDC_SCL
RGB_DDC_SDA
[PC_L_IN]
[PC_R_IN]
[SPDIF_OUT]
SPDIF
R
L
CVBS
AV DET
[AV1_R_IN]
[AV1_L_IN]
[AV1_CVBS_IN]
[AV1_CVBS_DET]
COMP_Y
COMP_P
COMP_P
COMP DE
COMP1
R
L
CVBS
AV DET
[AV1_R_IN]
[AV1_L_IN]
[AV1_CVBS_IN]
[AV1_CVBS_DET]
AV1
AV2
[ADAC_CR_P/N]
[SC_L/R_out P/N]
0V ~ 0.98V
0 OHM
COMP2 OPT
COMP2_R/G/B
0 OH
M
R
R
[GPIO]
[BSC_S_SCL]
[BSC_S_SDA]
BCM35230
(B0)
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