DOWNLOAD LG 55LW9500-TA (CHASSIS:LB12D) Service Manual ↓ Size: 18.76 MB | Pages: 115 in PDF or view online for FREE

Model
55LW9500-TA (CHASSIS:LB12D)
Pages
115
Size
18.76 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
55lw9500-ta-chassis-lb12d.pdf
Date
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3D sync
Backlight
Scanning signal
LEFT OPEN
RIGHT OPEN
Don’t need to control open time in Glasses
Backlight Scanning and Glasses
3D_SYNC_OUT
80P mini-LVDS Output 
RIGHT
80P mini-LVDS Output
LEFT
DDR3 SDRAM
- 
1Gbit (x16) 
- 800MHz
DDR3 SDRAM
-
1Gbit (x16)
-
800MHz
DDR1_DATA[15:0]
DDR1_A[12:0]/ 
BA[2:0]/CLK/CKE
DDR0_DATA[15:0]
DDR0_A[12:0]/ 
BA[2:0]/CLK/CKE
Vol. Regulator
(TPS51200)
Vol. Regulator
(TPS51200)
+1.5V1
+0.75V_VTT1
Vol. Regulator
(TPS51200)
Vol. Regulator
(TPS51200)
+1.5V0
+0.75V_VTT0
SPI_DO/CK/CS
SPI_DI
SPI FLASH
(4Mbit)
SPI FLASH
(4Mbit)
I2C_SDA
I2C_SCL
VCOMLOUT/ 
VCOMROUT
P_VCOM/ 
VCOMLFB/ 
VCOMRFB
DPM/FLK
PMIC
(TPS65168)
(0x42)
PMIC
(TPS65168)
(0x42)
VCC_LCM/VDD_LCM/ 
VGH/VGL/HVDD/VCORE
VLCD_POWER
+1.0V
DC-DC Converter
(AOZ1024DI)
DC-DC Converter
(AOZ1024DI)
VLCD_POWER
+3.3VD
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
VLCD_POWER
+2.5V
+3.3VD
LDO Regulator
(AP2132MP)
LDO Regulator
(AP2132MP)
Z_OUT
I2C_SDA
I2C_SCL
VCC_LCM/VDD_LCM/ 
HVDD
P-GAMMA
IC
(MAX9668B)
(0xE8)
P-GAMMA
IC
(MAX9668B)
(0xE8)
GMA[18:15], 
GMA[9:5]
P_VCOM
DDR3 SDRAM
- 
1Gbit (x16) 
- 800MHz
DDR3 SDRAM
-
1Gbit (x16)
-
800MHz
LG1121
 
(0x1C, direct
 
0xB2, in-direct)
XTAL_IN
XTAL_OUT
X-Tal 
(24.75Mhz)
FRC_RESET
XTR 
T-Con
 
(0x72)
I2C_SDA
I2C_SCL
I2C_TCON_SDA
I2C_TCON_SCL
EEPROM
(64kbit)
EEPROM
(64kbit)
Octa-link LVDS
VL
CD_P
OWE
R
(+1
2
V)
FR
C
_R
ES
ET
I2C
_SDA
I2C
_SCL
3D
_SY
N
C
_O
U
T
R_
VS
, M
2_
SC
LK/M
O
SI
I2C_SDA
I2C_SCL
2D
to
3D
(0x8E)
+3.3VD
+1.5V0
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
+3.3VD
+1.5V1
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
I2C_SDA
I2C_SCL
VCC_LCM/VDD_LCM/ 
HVDD
P-GAMMA
IC
(MAX9668B)
(0xEA)
P-GAMMA
IC
(MAX9668B)
(0xEA)
GMA[14:10], 
GMA[4:1]
Dual-link HF mini-LVDS
(@297MHz)
Dual-link HF mini-LVDS
(@297MHz)
Dual-link LVDS(@74.25MHz)
51Pin LVDS Input
+1.0VD
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
VLCD_POWER
GP3 Backend block diagram (SG)
DDR3 SDRAM
- 1Gbit (x16)
- 800MHz
DDR3 SDRAM
-
1Gbit (x16)
-
800MHz
DDR1_DATA[15:0]
DDR1_A[12:0]/ 
BA[2:0]/CLK/CKE
SPI_DO/CK/CS
SPI_DI
SPI FLASH
(4Mbit)
0X98
SPI FLASH
(4Mbit)
0X98
+1.5V
+3.3VD
LDO Regulator
(AP7173-SPG-13)
LDO Regulator
(AP7173-SPG-13)
URSA5
 
(0xB4)
LVDS data from 
Main IC 
( BCM35230 )
XTAL_IN
XTAL_OUT
X-Tal 
(24.75Mhz)
+12VD
+1.26V_FRC
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
Quad-link LVDS(@74.25MHz)
GP3 Backend block diagram (PG)
51Pin LVDS output
41Pin LVDS output
BCM35230
+12VD
+3.3V_FRC
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
Repair Guide for BCM Chassis
LG Electronics/ LCD TV 
JAN. 13
th
, 2011
Contents
0. ALEF & Edge LED, Overview models
1. Tool Option Information
2. Area Option Information
3. Main PCB for BroadBand
4. Formatter PCB for BroadBand
5. Block Diagram
6. Inner Connection
7. Repair Process (Troubleshooting)
By M.R.VIJAYSHANKAR
Model : **LW77/9500-TA, **LW57/6500-TA, **LV5500-TA
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