LG 55LM860V (CHASSIS:LD23E) Service Manual ▷ View online
Block Diagram
L9A
L9D
USB2.0x3
DDR3 X 3
16
16
16
eMMC
8
HDMI1
HDMI2
HDMI3
HDMI4
HDMI
(1 Ch)
CVBS
(
8
Ch)
Audio L/R
(5 Ch)
SIF(1 Ch)
CVBS-Out
SCART
Line-Out
SCART
Component
(2 Ch)
PC-RGB
(WUXGA)
I2S
CVBS(CHB)
TS In(CHB)
MICOM
IR
Keypad
HDMI
SW
RMII
PHY
SPIDF_OUT
Built-in WiFi
CI Slot
EB_DATA
Ethernet
TXA/B
51Pin LVDS
Motion-R
M-Remote_R/TX
AUD
BB_TP_DATA
CHB_DATA
DAC_DATA
AAD_DATA
HSR_P/M
DTV TS
Jack Interface
Main Chip
SC_DET
SC_CVBS_IN
DTV/MNT_V_OUT
MUX
IC2502
ATV_OUT
DTV/ATV_SELECT
SC_FB/ID_IN 2bit
SC_R/G/B 3bit
SC_L/R_IN
DSUB_R/G/B 3bit
DSUB_DET
RGB_DDC_SCL/SDA 2bit
Tuner
EEPROM
IC802/
R1EX24002ASAS0A
MICOM
EDID_WP
HP_L/ROUT
PC_L/R_IN
SPDIF_OUT
COMP_Y+/Pb+/Pr+
COMP_DET
AV_CVBS_IN
AV_L/R_IN
AV_CVBS_DET
SPDIF
PC_Audio
Earphone Block
RGB
SCART
ATSC Half NIM
DIF
SIF
Parallel TS
System
Demux
Demux
Audio DSP
Multi-STD
Audio Decoder
Multi-STD
Audio Decoder
BTSC AFE
10b@18.432MHz
w/ PLL
10b@18.432MHz
w/ PLL
1ch L/R
Audio-ADC
24b@48KHz
Audio-ADC
24b@48KHz
GBB AFE
1ch@30MHz
w/ PLL
1ch@30MHz
w/ PLL
Global Baseband
V/Q, DVB-T/C
V/Q, DVB-T/C
CVBS(6ch)
Component(2ch)
3ch Video
AFE
10b@165MHz
w/ LLPLL
AFE
10b@165MHz
w/ LLPLL
PC-RGB
HDMI-Rx 1.4
(1-port PHY)
3D, ARC, 4kx2k
(1-port PHY)
3D, ARC, 4kx2k
HDMI(1ch)
Capture
Block
(3CH)
Block
(3CH)
AAD
(THAT)
(THAT)
Audio Codec1
(Digital Part)
(Digital Part)
Mu
x
Analog Chip
Digital Chip
Audio L/R (5-ch)
SW
I2S(stero)
Sound
DSP
DSP
I2S
SPDIF
Video Decoder
(
(
Dual HD
)
CVBS AFE(2-ch)
12b@54MHz
12b@54MHz
12 : CVBS
Mu
x
12
Diplay
Engine
Engine
MC NR,
Vertical MC IPC
Vertical MC IPC
Scaler, PE
OSD, VCR
OSD, VCR
LVDS
H.264 Encoder
SD upto 480p
SD upto 480p
12
PHY
(3-port)
(3-port)
USB2.0
Host (x3)
Host (x3)
DDR3-PHY
DDR3(x16) * 3
Ethernet
MAC
MAC
eMMC
Controller
Controller
CPU
Dual C-A9 (1GHz)
Graphic
Engine
2D-VG / 3D Open-ES2.0
Audio
10(data)+1(en)+5(gc)
4(val, err, clk, sop)
+8 (data)
+8 (data)
I2C
I2C
6(gbb, l9da)
I2C
(Headphone)
Digital
Audio
Output
Audio
Output
LVDS
LVDS
Video
LVDS
Video
OSD
LVDS
Audio PLL
w/ DCO
w/ DCO
I2S (mono)
3(lrck, lrch, sck)
I2C
SW
SW
3D or UD
Data bridge
Data bridge
1 (ARC data)
ARC
(1ch)
I2S or SPDIF
8
Audio Clocks
9
1ch mono
Audio-ADC
24b@48KHz
Audio-ADC
24b@48KHz
Audio Codec0
(Digital Part)
(Digital Part)
Mu
x
LVDS
interrupt
3(hdmi, 3ch, gbb)
3(lrck, lrch, sck)
Audio
HDMI
(1-Link)
(1-Link)
I2S
Tuner_CVBS
L9 Block diagram
CPU
xi_main
1 Ghz
DDR3PLL
xo_main
1.6Ghz
DDR3PLL1
1.6Ghz
24Mhz
DDR3PLL2
0 1
0 1
0 1
CT
R
R
1/2
1/5
1.6Gh
z
z
1.6Ghz
Memory Controller
Memory Controller
Memory Controller
800Mhz
800Mhz
Video/Audio Block
CPU peripherial
CPU peripherial
dcoin_clk
DCO
DCO
200Mhz
200Mhz
Glitch-free logic
between
de_dco_out and
sdec_dco_out
de_dco_out and
sdec_dco_out
de_dco_ou
t
t
sdec_dco_o
ut
ut
0 1
CT
R
R
DISPLL
u_DPLL
udnt_buf_dpll_fin
disp_fout
Clock Divide & Reset
generation w/ test logic
DE
TE
sclk
27Mhz
27Mhz
27Mhz
27Mhz
2 port USB PHY
1 port USB PHY
30/48Mhz
30/48 Mhz
i_core800_clk
i_core320_clk
i_m01_ddrclk
i_m2_ddrclk
u_crg
Clock Divide & Reset generation
w/ test logic
w/ test logic
Clock Divide & Reset generation
w/ test logic
w/ test logic
Clock Divide & Reset generation
w/ test logic
w/ test logic
Clock Divide & Reset generation
w/ test logic
w/ test logic
Clock Divide & Reset generation
w/ test logic
w/ test logic
USB controller
About 220 internally generated clocks
SSC setting
- 0xFD3001CC
- 0xFD3001D0
- 0xFD3001CC
- 0xFD3001D0
SSC setting
- 0xFD3001C4
- 0xFD3001D8
- 0xFD3001C4
- 0xFD3001D8
SSC setting
-
0xFD300108
-
0xFD30010C
SSC setting
- 0xFD3001D4
- 0xFD3001D8
- 0xFD3001D4
- 0xFD3001D8
L9 Block diagram
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