LG 47LM8600 / 47LM8650 (CHASSIS:LA23E) Service Manual ▷ View online
Main PCB for Broadband
Main + TCON all in one
To PSU
To FRC BOARD
1
3
4
1
Main processor_Digital(LG1152D),
DDR Memory
Flash Memory
DDR Memory
Flash Memory
2
3
4
Micom for Key/IR sensing
HDMI switch (4:1)
Audio AMP (10W+10W)
XXLM9600-NA
wifi
Local Key +IR
Motion assy
Front Spk
Woofer Spk
Local Dim.
2
4
Main processor_analog(LG1152A)
5
3D Depth Control IC,
DDR Memory
DDR Memory
6
5
6
FRC Board for Broadband
Main + TCON all in one
1
FRC Processor(LG1122)
2
XXLM9600-NA
T-Con IC(LG5812)
1
2
From Main Board
To Pannel ( Left )
To Pannel ( Right )
L9
LG1152D
LG1152D
AUD
BB_TP_DATA
DAC_DATA
AAD_DATA
HSR_P/M
CVBS
DIF(P/N)
SIF
Tuner
PC_AUDIO
PC_Audio L/R
AV 1_Audio L/R
Comp 1_Audio L/R
PC-
RGB
A/V1
COMP1
A/V1_CVBS
Comp1 Y,Pb,Pr
PC_R,G,B,H,V
HDMI
Switch
Switch
HDMI1~4
L9
LG1152A
LG1152A
USB1
USB2
USB3
USB
HUB
HUB
PHY
RMII
LAN
Motion-R
M-Remote_R/TX
Audio
AMP
AMP
OPTIC
SPK
H/P
H/P Audio L/R
SPDIF
I2S
16
DDR
16
DDR
256MB×4
(1600)
(1600)
128MB×1
(1600)
(1600)
8
eMMC
4GB×1
Built-in WiFi
3D
Depth
LG1132
Depth
LG1132
FRC-III
LG1122
LG1122
mini_LVDS
mini_LVDS
T-con
LG5812
LG5812
HS_LVDS
2Link
HS_LVDS / 2Link
V by One / 8 Line
CHB_DATA
L9 Block diagram
ATSC Half NIM
DIF
SIF
Parallel TS
System
Demux
Demux
Audio DSP
Multi-STD
Audio Decoder
Multi-STD
Audio Decoder
1ch L/R
Audio-ADC
24b@48KHz
Audio-ADC
24b@48KHz
GBB AFE
1ch@30MHz
w/ PLL
1ch@30MHz
w/ PLL
Global Baseband
V/Q, DVB-T/C
V/Q, DVB-T/C
CVBS(6ch)
Component(2ch)
3ch Video
AFE
10b@165MHz
w/ LLPLL
AFE
10b@165MHz
w/ LLPLL
PC-RGB
HDMI-Rx 1.4
(1-port PHY)
3D, ARC, 4kx2k
(1-port PHY)
3D, ARC, 4kx2k
HDMI(1ch)
Capture
Block
(3CH)
Block
(3CH)
AAD
(THAT)
(THAT)
Audio Codec1
(Digital Part)
(Digital Part)
Mu
x
Analog Chip
Digital Chip
Audio L/R (5-ch)
SW
I2S(stero)
Sound
DSP
DSP
I2S
SPDIF
Video Decoder
(
(
Dual HD
)
CVBS AFE(2-ch)
12b@54MHz
12b@54MHz
12 : CVBS
Mu
x
12
Diplay
Engine
Engine
MC NR,
Vertical MC IPC
Vertical MC IPC
Scaler, PE
OSD, VCR
OSD, VCR
LVDS
H.264 Encoder
SD upto 480p
SD upto 480p
12
PHY
(3-port)
(3-port)
USB2.0
Host (x3)
Host (x3)
DDR3-PHY
DDR3(x16) * 3
Ethernet
MAC
MAC
eMMC
Controller
Controller
CPU
Dual C-A9 (1GHz)
Graphic
Engine
2D-VG / 3D Open-ES2.0
Audio
10(data)+1(en)+5(gc)
4(val, err, clk, sop)
+8 (data)
+8 (data)
I2C
I2C
6(gbb, l9da)
I2C
(Headphone)
Digital
Audio
Output
Audio
Output
LVDS
LVDS
Video
LVDS
Video
OSD
LVDS
Audio PLL
w/ DCO
w/ DCO
I2S (mono)
3(lrck, lrch, sck)
I2C
SW
SW
3D or UD
Data bridge
Data bridge
1 (ARC data)
ARC
(1ch)
I2S or SPDIF
8
Audio Clocks
9
1ch mono
Audio-ADC
24b@48KHz
Audio-ADC
24b@48KHz
Audio Codec0
(Digital Part)
(Digital Part)
Mu
x
LVDS
interrupt
3(hdmi, 3ch, gbb)
3(lrck, lrch, sck)
Audio
HDMI
(1-Link)
(1-Link)
I2S
Tuner_CVBS
L9 Block diagram
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