LG 47LE8500 (CHASSIS:LA02E) Service Manual ▷ View online
* Each of analog audio signals shall be designed with “Common Mode (INCM) signal ”
2. Video Signal block
D-sub RGB
HDMI 1
SIDE_CVBS Phone JACK
CVBS(SIDE_AV_CVBS)
B(DSUB_B)
REAR AV
Component 1
CVBS(REAR_AV_CVBS)
Component 2
Y(COMP2_Y)
H_sync(RGB_HSYNC)
Pb(COMP2_Pb)
Pr(COMP2_Pr)
Y(COMP1_Y)
Pb(COMP1_Pb)
Pr(COMP1_Pr)
G(DSUB_G)
R(DSUB_R)
HDMI_RX0+/-, RX1+/-, RX2 +/-, CLK +/-
HDMI_SDA
HDMI_SCL
LGE3549
SD_CVBS2
SD_CVBS3
SD_Y1
SD_PB1
SD_PR1
SD_Y2
SD_PB2
SD_PR2
SD_B
SD_R
SD_G
RGB_HSYNC
RGB_VSYNC
HDMI_RX_0_CLK_P
HDMI_RX_0_CLK_N
HDMI_RX_0_DATA0_P
HDMI_RX_0_DATA0_N
HDMI_RX_0_DATA1_P
HDMI_RX_0_DATA1_N
HDMI_RX_0_DATA2_P
HDMI_RX_0_DATA2_N
HDMI_RX_0_CLK_N
HDMI_RX_0_DATA0_P
HDMI_RX_0_DATA0_N
HDMI_RX_0_DATA1_P
HDMI_RX_0_DATA1_N
HDMI_RX_0_DATA2_P
HDMI_RX_0_DATA2_N
HDMI_RX_0_DDC_SCL
HDMI_RX_0_DDC_SDA
HDMI_RX_0_RESREF
HDMI_RX_1_RESREF
499Ω_1%
499Ω_1%
A2.5VI
TMDS
DDC
HPD_1
HDMI 2
HDMI 3
HDMI 4
HDMI
4x1
Switch
(TDA19997)
IF + [MAIN]
CVBS [MAIN]
IF - [MAIN]
EDSAFE_IF_P
EDSAFE_IF_N
EDSAFE_IF_N
SD_CVBS1
V_sync(RGB_VSYNC)
TMDS
DDC
HPD_2
TMDS
DDC
HPD_3
TMDS
DDC
HPD_4
GPIO-18
GPIO_17
GPIO_19
GPIO_53
RF
SIDE_Component Phone Jack
Y(SIDE_COMP-Y)
Pb(SIDE_COMP-Pb)
Pr(SIDE_COMP-Pr)
SD_Y3
SD_PB3
SD_PR3
TDVJ-H031F
Main tuner
* Each of analog signals shall be designed with “Common Mode (INCM) signal ”
3. Audio Signal block
BCM3549
TR
Buffer
SIF
LGE3549
AUDMX_LEFT1
AUDMX_RIGHT1
AUDMX_RIGHT1
AUD_SPDIF
ATSC/NTSC
TDVJ-001F
TDVJ-031F
TDVJ-031F
ATSC/NTSC
TDVJ-001F
TDVJ-031F
TDVJ-031F
MUTE
From Micom
From Micom
I2S_CLK_OUT
I2S_DATA_OUT
I2S_LR_OUT
NTP7000
NTP7000
SPDIF_OUT
I2S
HP_L/R
TPA6132
(HP AMP)
TPA6132
(HP AMP)
SD_SIF1
AV1 Audio (Rear)
REAR_AV_L_IN
REAR_AV_R_IN
AUDMX_LEFT3
AUDMX_RIGHT3
AUDMX_RIGHT3
Comp1 Audio (Rear)
COMP1_L_IN
COMP1_R_IN
AUDMX_LEFT2
AUDMX_RIGHT2
AUDMX_RIGHT2
Comp2 Audio (Rear)
AUDMX_LEFT4
AUDMX_RIGHT4
AUDMX_RIGHT4
(1) IOP, Edge LED models
AV2 or Comp3 Audio
(Used in common)
(Used in common)
(2) Lamp models
AV2 Audio
SIDE_AV_L_IN
SIDE_AV_R_IN
COMP2_L_IN
COMP2_R_IN
RGB-PC Audio
AUDMX_LEFT5
AUDMX_RIGHT5
AUDMX_RIGHT5
PC_L_IN
PC_R_IN
MAX17113
(4CH DCDC converter)
TPS62110
(DCDC converter for HVDD)
MAX9668
(P_GAMMA, VCOM)
MAX17119
(Level shifter)
Vin_12
V
V
T-CON
SoC
(LG5111
or
LGE7378A)
Enable1 for
Vcc Vgl
Enable2 (DPM) for
Vgh Vdd
I2C(SCL3& SDA3_3.3V)
From LGE3549
GCLK / VDD_EVEN_ODD/VST
(3.3V level)
Enable2 (DPM) for
HVDD
Vin_12V
Vgh_28
V
V
Vdd_16
V
V
Vcc_3.3V
HVDD
Vgl_-5V
Source Driver IC
HVDD
Vdd
Vcc
GMA (gamma voltage)
V-COM
GCLK / VDD_EVEN_ODD/VST
(33V level)
60
pin
60
pin
Left / Right mini-LVDS 6pairs
GCLK / VDD_EVEN_ODD/VST (33V level)
VCOM / GMA (gamma voltage)
Vgh / Vdd /
Vcc / Vgl /
HVDD
T_con signal ( POL / SOE )
4. M+S block
LVDS_TX_0_CLK
LVDS_TX_1_CLK
LVDS_TX_0_DATA
LVDS_TX_1_DATA
LGE35
49
5. FRC (URSA3 – LGE7378A) block with LG5111
I2C3_3.3V
LGE7378A (FRC)
S-Flash
(4MBIT)
DDR3
(1GBIT)
HW option
Dual Display
Control with
120Hz
(FRC)
LVDS Serial I/F (data[10]+clk[2])
LVDS Serial I/F (data[10]+clk[2])
LVDS Serial I/F (data[10]+clk[2])
LVDS Serial I/F (data[10]+clk[2])
LG51111
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