DOWNLOAD LG 47LD920 (CHASSIS:LD01I) Service Manual ↓ Size: 9.42 MB | Pages: 112 in PDF or view online for FREE

Model
47LD920 (CHASSIS:LD01I)
Pages
112
Size
9.42 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
47ld920-chassis-ld01i.pdf
Date
PREV: LG 47LD750 / 47LD750N / 47LD751 / 47LD780 / 47LD790 (CHASSIS:LD03B) Service Manual

LG 47LD920 (CHASSIS:LD01I) Service Manual ▷ View online

[E1]
[D1]
[L9]
[N5]
[N4]
[N12]
[N13]
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
URSA_B2P
URSA_B2M
URSA_BCKP
URSA_BCKM
URSA_B3P
URSA_B3M
URSA_B4P
URSA_B4M
URSA_C0P
URSA_C0M
URSA_C1P
URSA_C1M
URSA_C2P
URSA_C2M
URSA_D1M
URSA_D1P
URSA_D0M
URSA_D0P
URSA_C4M
URSA_C4P
URSA_C3M
URSA_C3P
URSA_CCKM
URSA_CCKP
URSA_D2P
URSA_D2M
URSA_DCKP
URSA_DCKM
URSA_D3P
URSA_D3M
URSA_D4P
URSA_D4M
URSA_A0P
URSA_A0M
URSA_A1P
URSA_A1M
URSA_A2P
URSA_A2M
URSA_ACKP
URSA_ACKM
URSA_A3P
URSA_A3M
URSA_A4P
URSA_A4M
URSA_B0P
URSA_B0M
URSA_B1P
URSA_B1M
URSA_A[0]
URSA_A[2]
URSA_A[4]
URSA_A[6]
URSA_A[8]
URSA_A[11]
URSA_A[1]
URSA_A[10]
URSA_A[5]
URSA_A[9]
URSA_A[12]
URSA_A[7]
URSA_A[3]
URSA_DQ[0-31]
URSA_DQ[20]
URSA_DQ[19]
URSA_DQ[17]
URSA_DQ[22]
URSA_DQ[27]
URSA_DQ[28]
URSA_DQ[25]
URSA_DQ[30]
URSA_DQ[31]
URSA_DQ[24]
URSA_DQ[26]
URSA_DQ[29]
URSA_DQ[23]
URSA_DQ[16]
URSA_DQ[18]
URSA_DQ[21]
URSA_DQ[4]
URSA_DQ[3]
URSA_DQ[1]
URSA_DQ[6]
URSA_DQ[11]
URSA_DQ[12]
URSA_DQ[9]
URSA_DQ[14]
URSA_DQ[15]
URSA_DQ[8]
URSA_DQ[10]
URSA_DQ[13]
URSA_DQ[7]
URSA_DQ[0]
URSA_DQ[2]
URSA_DQ[5]
URSA_B4P
URSA_B3M
URSA_B3P
URSA_BCKM
URSA_BCKP
URSA_B2M
URSA_B2P
URSA_B1M
URSA_B1P
URSA_B0M
URSA_B0P
URSA_A4M
URSA_A4P
URSA_A3M
URSA_A3P
URSA_ACKM
URSA_ACKP
URSA_A2M
URSA_A2P
URSA_A1M
URSA_A1P
URSA_A0M
URSA_A0P
URSA_D4M
URSA_D4P
URSA_D3M
URSA_D3P
URSA_DCKM
URSA_DCKP
URSA_D2M
URSA_D2P
URSA_D1M
URSA_D1P
URSA_D0M
URSA_D0P
URSA_C4M
URSA_C4P
URSA_C3M
URSA_C3P
URSA_C0P
URSA_C0M
URSA_CCKM
URSA_CCKP
URSA_C2M
URSA_C2P
URSA_C1M
URSA_C1P
URSA_B4M
+3.3V_MEMC
L902
BLM18PG121SN1D
+1.8V_FRC_DDR
MEMC_RXE1+
MEMC_RXE1-
MEMC_RXE3+
MEMC_RXE2+
MEMC_RXE3-
MEMC_RXE2-
MEMC_RXO0-
MEMC_RXEC+
MEMC_RXO1-
MEMC_RXO1+
MEMC_RXE4+
MEMC_RXO0+
MEMC_RXEC-
MEMC_RXE4-
MEMC_RXO4-
MEMC_RXO3+
MEMC_RXOC-
MEMC_RXOC+
MEMC_RXO2+
MEMC_RXO4+
MEMC_RXO3-
MEMC_RXO2-
PANEL_POWER
+3.3V_MEMC
+3.3V_MEMC
+3.3V_MEMC
MEMC_RESET
URSA_RASZ
URSA_CASZ
URSA_WEZ
URSA_BA1
URSA_BA0
URSA_MCLKE
URSA_DQM1
URSA_DQM0
URSA_DQS0
URSA_DQSB0
URSA_DQS1
URSA_DQSB1
URSA_MCLK1
URSA_MCLKZ1
URSA_DQM3
URSA_DQM2
URSA_DQS2
URSA_DQSB2
URSA_DQS3
URSA_DQSB3
URSA_MCLK
URSA_MCLKZ
URSA_ODT
URSA_DQ[0-31]
URSA_A[0-12]
M_XTALI
M_XTALO
M_XTALO
M_XTALI
M_SPI_CZ
M_SPI_DO
M_SPI_CK
M_SPI_DI
M_SPI_CZ
M_SPI_DO
M_SPI_DI
M_SPI_CK
+3.3V_MEMC
R954
820
R930
100
R943
100
R938
100
R946
100
R935
100
R945
100
R929
100
R942
100
R936
100
R928
100
MEMC_SDA
MEMC_SCL
L904
BLM18PG121SN1D
L905
BLM18PG121SN1D
MEMC_RXE0+
MEMC_RXE0-
C913
10uF
C917
10uF
C914
10uF
C916
10uF
10V
C908
10uF
10V
C909
22uF
16V
C912
22uF
16V
IC902
W25X20AVSNIG
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
+3.3V_MEMC
R992
100
R993
100
+3.3V_MEMC_AVDD
+3.3V_MEMC
+3.3V_MEMC
+3.3V_MEMC
X900
12MHz
L907
CB3216PA501E
PWM_DIM
OPC_EN
OPC_OUT1
C907
10uF
OPC_OUT2
+1.26V_MEMC
WP_FLASH_MEMC
C902
15pF
C900
15pF
R934
1M
R931
100
R939
100
+3.3V_MEMC_AVDD
WP_FLASH_MEMC
R941
1K
OPT
R956
1K
R940
1K
OPT
+3.3V_MEMC
R957
1K
R953
0
R933
0
OPT
R979
0
R973
0
OPT
R971
0
OPT
R937
0
32"_OPC2_OFF
R978
4.7K
OPT
R970
4.7K
OPT
C
9
0
3
0
.
1
u
F
C956
0.1uF
C
9
0
4
0
.
1
u
F
C953
0.1uF
C
9
1
8
0
.
1
u
F
C
9
3
5
0.1uF
C
9
3
2
0.1uF
C
9
3
8
0
.
1
u
F
C950
0.1uF
C
9
4
1
0
.
1
u
F
C
9
3
4
0.1uF
C919
0.1uF
C949
0.1uF
C947
0.1uF
C920
0.1uF
C
9
3
7
0
.
1
u
F
C
9
4
4
0
.
1
u
F
C923
0.1uF
C929
0.1uF
C928
0.1uF
C925
0.1uF
C
9
3
6
0.1uF
C927
0.1uF
C
9
3
9
0
.
1
u
F
C
9
4
5
0
.
1
u
F
C926
0.1uF
C
9
3
3
0.1uF
C922
0.1uF
C921
0.1uF
C952
1000pF
R927
10K
R951
10K
R952
10K
R994
10K
R960
1K
OPT
R959
1K
R964
1K
OPT
R963
1K
R949
1K
R950
1K
OPT
C924
1uF
C906
1uF
R925
56
R947
56
R948
56
R926
56
P900
TF05-51S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
P901
TF05-41S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
C957
0.1uF
OPT
C958
0.1uF
OPT
C959
0.1uF
OPT
C960
0.1uF
OPT
C961
0.1uF
OPT
C962
0.1uF
OPT
C963
0.1uF
OPT
C964
0.1uF
OPT
L903
BLM18PG121SN1D
C901
10uF
10V
C905
10uF
10V
IC900
LGE7329A
E1
SDAS
D1
SCLS
F1
GPIO[8]
G1
GPIO[9]
K8
GND_14
E5
VDDC_1
E2
GPIO[10]
F2
GPIO[11]
F3
GPIO[12]
G2
GPIO[13]
M4
GPIO[22]
M5
GPIO[23]
G3
GPIO[14]
E4
GPIO[15]
F4
GPIO[16]
G4
GPIO[17]
H4
GPIO[18]
J4
GPIO[19]
K4
GPIO[20]
L4
GPIO[21]
J6
VDDP_2
H9
GND_7
F6
VDDC_2
H1
MDATA[20]
H2
MDATA[19]
H3
MDATA[17]
J1
MDATA[22]
J2
MDATA[27]
J3
MDATA[28]
K1
MDATA[25]
K2
MDATA[30]
K6
AVDD_DDR_2
K3
DQM[3]
L1
DQM[2]
J8
GND_10
L2
DQS[2]
L3
DQSB[2]
L6
AVDD_DDR_4
L8
VDDP_3
H10
GND_8
M1
DQS[3]
M2
DQSB[3]
L7
AVDD_DDR_5
M3
MDATA[31]
N1
MDATA[24]
J9
GND_11
N2
MDATA[26]
N3
MDATA[29]
L10
AVDD_DDR_6
P1
MDATA[23]
R1
MDATA[16]
T1
MDATA[18]
T2
MDATA[21]
R2
MCLK[0]
P2
MCLKZ[0]
G7
GND_1
L9
AVDD_MEMPLL
N5
MVREF
N4
ODT
T3
RASZ
R3
CASZ
P3
MADR[0]
T4
MADR[2]
R4
MADR[4]
J10
GND_12
P4
MADR[6]
T5
MADR[8]
R5
MADR[11]
P5
WEZ
T6
BADR[1]
R6
BADR[0]
P6
MADR[1]
T7
MADR[10]
L11
AVDD_DDR_7
R7
MADR[5]
P7
MADR[9]
T8
MADR[12]
R8
MADR[7]
P8
MADR[3]
N8
MCLKE
K10
GND_16
F7
VDDC_3
T9
MDATA[4]
R9
MDATA[3]
K7
GND_13
P9
MDATA[1]
T10
MDATA[6]
K11
AVDD_DDR_3
R10
MDATA[11]
P10
MDATA[12]
T11
MDATA[9]
R11
MDATA[14]
J11
AVDD_DDR_1
P11
DQM[1]
T12
DQM[0]
R12
DQS[0]
P12
DQSB[0]
H11
VDDP_1
T13
DQS[1]
R13
DQSB[1]
P13
MDATA[15]
T14
MDATA[8]
R14
MDATA[10]
P14
MDATA[13]
T15
MDATA[7]
R15
MDATA[0]
P15
MDATA[2]
T16
MDATA[5]
R16
MCLK[1]
P16
MCLKZ[1]
N9
GPIO[26]
N10
GPIO[27]
N11
GND_17
M11
RESET
G6
VDDC_4
N12
GPIO[28]
N13
GPIO[29]
N14
GPIO[30]
L13
SCK
M13
SDI
M12
SDO
K13
CSZ
L12
PWM1
K12
PWM0
J13
GPIO[0]
H13
GPIO[1]
G13
GPIO[2]
F13
GPIO[3]
E13
GPIO[4]
F12
GPIO[5]
D14
GPIO[6]
E12
GPIO[7]
N6
GPIO[24]
H6
VDDC_5
N15
LVD4M
N16
LVD4P
M14
LVD3M
M15
LVD3P
F8
AVDD_33_1
M16
LVDCKM
L16
LVDCKP
L15
LVD2M
L14
LVD2P
G9
GND_3
K14
LVD1M
J14
LVD1P
J16
LVD0M
J15
LVD0P
H15
LVC4M
H16
LVC4P
H14
LVC3M
G14
LVC3P
G16
LVCCKM
G15
LVCCKP
F15
LVC2M
F16
LVC2P
F14
LVC1M
E14
LVC1P
E16
LVC0M
E15
LVC0P
G10
GND_4
F9
AVDD_33_2
D16
LVB4M
D15
LVB4P
C16
LVB3M
B16
LVB3P
A16
LVBCKM
A15
LVBCKP
B15
LVB2M
C15
LVB2P
D2
GPIO_3
E3
GPIO_10
E10
GPIO_11
D10
GPIO_7
D8
GPIO_5
D12
REXT
C14
LVB1M
C13
LVB1P
A13
LVB0M
B13
LVB0P
D7
GPIO_4
D9
GPIO_6
B12
LVA4M
A12
LVA4P
C12
LVA3M
C11
LVA3P
A11
LVACKM
B11
LVACKP
B10
LVA2M
A10
LVA2P
C10
LVA1M
C9
LVA1P
A9
LVA0M
B9
LVA0P
F10
AVDD_PLL
G8
GND_2
D11
GPIO_8
D13
GPIO_9
E11
GPIO_12
N7
GPIO[25]
D6
SCLM
D5
SDAM
A14
GPIO_1
B14
GPIO_2
D3
XIN
D4
XOUT
K16
GPIO_14
K15
GPIO_13
H7
GND_5
G11
AVDD_LVDS_2
B8
RO0N
A8
RO0P
C8
RO1N
C7
RO1P
A7
RO2N
B7
RO2P
B6
ROCKN
A6
ROCKP
C6
RO3N
C5
RO3P
A5
RO4N
B5
RO4P
H8
GND_6
F11
AVDD_LVDS_1
B4
RE0N
A4
RE0P
C4
RE1N
C3
RE1P
A3
RE2N
B3
RE2P
B2
RECKN
A2
RECKP
C2
RE3N
C1
RE3P
A1
RE4N
B1
RE4P
GND_9
J7
GND_15
K9
R
9
7
2
4
7
0
OPT
L908
BLM18PG121SN1D
37"42"47"_OPC2
L909
BLM18PG121SN1D
L910
BLM18PG121SN1D
L911
BLM18PG121SN1D
C951
10uF
16V
OPT
R961
0
3D_POWER_EN
R958
0
3D_SCL
/3D_FPGA_RESET
R955
0
3D_SDA
PANEL_POWER
L901
CB3216PA501E
C965
10uF
16V
OPT
C967
0.1uF
16V
C966
1000pF
50V
MDS61887706
M3
OPT
MDS61887706
M4 37"42"47"_EMI
MDS61887706
M1
OPT
MDS61887706
M2
OPT
SPI FLASH
XTAL
MST7329N(FRC)
12
9
GPIO8
HIGH
HIGH
I2C
EEPROM
SPI
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
PWM1
PWM0
Placed on SMD-TOP
Placed on SMD-TOP
GPIO12
LOW
GPIO14
VENUS (MST7329N)
HIGH
URSAII MINI LVDS TYPE
LOW
URSAII LVDS TYPE
LOW
M+S NORMAL 42"(MST7327N)
LOW
HIGH
URSAII MINI LVDS TYPE
HIGH
HIGH
URSAII MINI LVDS TYPE
M+S GIP 37"(MST7327N)
M+S NORMAL 47"(MST7327N)
CONTACT TO MODULE FOR EMI
EAX57644502
   2009.05.15
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
DDR_DQ[16-31]
DDR_DQ[16]
DDR_DQ[17]
DDR_DQ[18]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[21]
DDR_DQ[22]
DDR_DQ[23]
DDR_DQ[24]
DDR_DQ[25]
DDR_DQ[26]
DDR_DQ[27]
DDR_DQ[28]
DDR_DQ[29]
DDR_DQ[30]
DDR_DQ[31]
DDR_DQ[27]
DDR_DQ[28]
DDR_DQ[25]
DDR_DQ[30]
DDR_DQ[22]
DDR_DQ[17]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[31]
DDR_DQ[24]
DDR_DQ[26]
DDR_DQ[29]
DDR_DQ[23]
DDR_DQ[16]
DDR_DQ[18]
DDR_DQ[21]
DDRB_A[0-12]
DDRB_A[0]
DDRB_A[1]
DDRB_A[2]
DDRB_A[3]
DDRB_A[4]
DDRB_A[5]
DDRB_A[6]
DDRB_A[7]
DDRB_A[8]
DDRB_A[9]
DDRB_A[10]
DDRB_A[11]
DDRB_A[12]
DDRB_A[10]
DDRB_A[1]
DDRB_A[9]
DDRB_A[12]
DDRB_A[7]
DDRB_A[5]
DDRB_A[0]
DDRB_A[2]
DDRB_A[4]
DDRB_A[6]
URSA_DQ[27]
URSA_DQ[28]
URSA_DQ[25]
URSA_DQ[30]
URSA_DQ[22]
URSA_DQ[17]
URSA_DQ[19]
URSA_DQ[20]
URSA_DQ[31]
URSA_DQ[24]
URSA_DQ[26]
URSA_DQ[29]
URSA_DQ[23]
URSA_DQ[16]
URSA_DQ[18]
URSA_DQ[21]
URSA_A[10]
URSA_A[1]
URSA_A[9]
URSA_A[12]
URSA_A[7]
URSA_A[5]
URSA_A[0]
URSA_A[2]
URSA_A[4]
URSA_A[6]
DDRA_A[2]
URSA_DQ[4]
DDR_DQ[11]
DDRA_A[1]
URSA_DQ[6]
DDR_DQ[10]
DDRA_A[0]
DDR_DQ[9]
DDR_DQ[8]
DDR_DQ[7]
URSA_DQ[14]
URSA_DQ[2]
DDR_DQ[6]
URSA_DQ[9]
DDR_DQ[5]
URSA_DQ[0]
DDR_DQ[4]
URSA_DQ[7]
DDRA_A[0-12]
DDRA_A[4]
DDR_DQ[3]
DDR_DQ[4]
DDRA_A[6]
DDR_DQ[2]
URSA_DQ[12]
URSA_DQ[11]
DDR_DQ[3]
DDRA_A[0]
DDR_DQ[1]
DDRA_A[2]
DDR_DQ[1]
DDR_DQ[0]
DDRA_A[5]
DDR_DQ[6]
DDRA_A[7]
DDR_DQ[14]
URSA_DQ[5]
URSA_DQ[15]
DDRA_A[12]
DDR_DQ[9]
DDRA_A[9]
DDR_DQ[12]
DDR_DQ[11]
DDRA_A[10]
DDR_DQ[5]
DDRA_A[1]
DDR_DQ[2]
DDR_DQ[0]
DDRA_A[12]
DDR_DQ[0-15]
URSA_DQ[3]
DDR_DQ[7]
DDRA_A[11]
DDR_DQ[13]
DDRA_A[10]
URSA_DQ[10]
DDR_DQ[10]
DDRA_A[9]
URSA_DQ[8]
DDR_DQ[8]
DDRA_A[8]
DDR_DQ[15]
DDRA_A[7]
DDR_DQ[15]
DDRA_A[6]
URSA_DQ[13]
DDRA_A[5]
DDR_DQ[14]
DDRA_A[4]
DDR_DQ[13]
DDRA_A[3]
URSA_DQ[1]
DDR_DQ[12]
DDRA_A[3]
URSA_A[3]
URSA_A[1]
URSA_A[10]
URSA_A[9]
URSA_A[12]
URSA_A[7]
URSA_A[5]
URSA_A[2]
URSA_A[0]
URSA_A[6]
URSA_A[4]
DDRB_A[11]
DDRB_A[8]
DDRA_A[8]
DDRA_A[11]
URSA_A[11]
URSA_A[8]
URSA_A[8]
URSA_A[11]
URSA_A[3]
DDRB_A[3]
AR1000
56
AR1002
56
AR1001
56
AR1003
56
AR1013
22
AR1014
22
AR1015
22
URSA_DQ[0-31]
010:AL20;009:AB4
R1000
150
OPT
AR1006
56
AR1005
56
AR1007
56
AR1010
22
AR1004
56
AR1011
22
AR1012
22
R1039
150
OPT
URSA_DQ[0-31]
010:E20;009:AB4
URSA_A[0-12]
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
R1025
22
R1027
22
R1008
22
R1024
22
R1005
22
R1006
22
R1033
56
R1034
56
R1032
56
R1014
56
R1031
56
R1015
56
R1012
56
R1035
56
R1016
56
R1036
56
R1017
56
R1013
56
C1023
10uF
C1028
10uF
C1002
10uF
AR1016
22
AR1017
22
URSA_MCLKZ
009:J10
URSA_BA1
010:T9;009:R4
URSA_WEZ
010:T8;009:R4
URSA_RASZ
URSA_DQM3
009:J15
URSA_MCLKE
010:T9;009:T4
URSA_DQSB3
009:J13
URSA_ODT
010:Y14;009:J10
URSA_CASZ
URSA_DQM2
009:J15
B_URSA_BA0
URSA_BA0
010:T9;009:S4
URSA_DQS2
009:J14
B_URSA_BA1
URSA_MCLK
009:J11
URSA_DQS3
009:J13
URSA_DQSB2
009:J14
B_URSA_MCLKE
010:T10
B_URSA_WEZ
010:T10
B_URSA_BA1
B_URSA_BA0
B_URSA_WEZ
010:Q13
B_URSA_MCLKE
010:Q14
B_URSA_RASZ
010:R16
B_URSA_CASZ
010:R16
B_URSA_RASZ
B_URSA_CASZ
AR1018
22
AR1019
22
A_URSA_BA1
010:AA15
A_URSA_BA0
010:AA15
A_URSA_MCLKE
010:Z14
A_URSA_WEZ
010:Y13
URSA_BA0
010:V10;009:S4
URSA_BA1
010:V10;009:R4
URSA_WEZ
010:V10;009:R4
URSA_MCLKE
010:V10;009:T4
A_URSA_RASZ
A_URSA_CASZ
URSA_RASZ
URSA_CASZ
A_URSA_MCLKE
010:V9
URSA_MCLKZ1
009:AB4
URSA_DQS0
009:X4
A_URSA_CASZ
010:X16
URSA_DQSB0
009:X4
URSA_DQM1
009:W4
A_URSA_BA1
A_URSA_BA0
A_URSA_RASZ
010:X16
URSA_MCLK1
009:AB4
A_URSA_WEZ
010:V8
URSA_ODT
010:Q14;009:J10
URSA_DQS1
009:Y4
URSA_DQM0
009:X4
URSA_DQSB1
009:Y4
C1001
10uF
10V
C1022
10uF
10V
R1002
1K
1%
R1038
1K
1%
R1001
1K
1%
R1037
1K
1%
C1020
0.1uF
C1016
0.1uF
C1007
0.1uF
C1015
0.1uF
C1009
0.1uF
C1018
0.1uF
C1004
0.1uF
C1025
0.1uF
C1026
0.1uF
C1012
0.1uF
C1027
0.1uF
C1005
0.1uF
C1019
0.1uF
C1011
0.1uF
C1003
0.1uF
C1006
0.1uF
C1017
0.1uF
C1024
0.1uF
C1014
0.1uF
C1013
0.1uF
C1039
0.1uF
C1038
0.1uF
C1029
0.1uF
C1041
0.1uF
C1037
0.1uF
C1031
0.1uF
C1040
0.1uF
C1034
0.1uF
C1033
0.1uF
C1036
0.1uF
C1035
0.1uF
C1030
0.1uF
C1010
0.1uF
IC1000
H5PS5162FFR-S6C
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
IC1001
H5PS5162FFR-S6C
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR2 1.8V By CAP - Place these Caps near Memory
MST7327N DDR2
10
12
EAX57644502
2009.05.15
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
ASDO
DATA0
/CSO
/CONFIG
/STATUS
DCLK
/CE
CONFIG_DONE
2V5
R134
1K
L101
BLM18PG121SN1D
X100
54.0000MHz
4
VDD
1
TRISTATE/OPEN
2
GND
3
OUTPUT
DCLK
R119
22
SYSCLK
2V5
R121
22
/STATUS
C116
10uF
16V
R120
27
R131
10K
/CE
R133
10K
ASDO
IC101
EPCS16SI8N_
3
VCC
2
DATA
4
GND
1
NCS
5
ASDI
6
DCLK
7
VCC_1
8
VCC_2
C118
100pF
50V
R132
10K
2V5
C121
0.1uF
16V
R130
10K
C117
0.1uF
16V
R122
22
/CONFIG
R117
22
/CSO
C119
10pF
DATA0
RD2+
RA1+
RB2-
RE2-
RC2-
RA2-
RA1-
RC2+
RA2+
RB2+
RE2+
RD2-
RE1+
RE3+
RB4-
RD3-
RCLK1+
RA4+
RE4-
RE4+
RD4+
RC4+
RD1-
RA3+
RE3-
RB1+
RA4-
RD4-
RC4-
RA3-
RCLK4-
RB4+
RCLK4+
RB3+
RC1+
RB1-
RC3+
RE1-
RCLK1-
RB3-
RD3+
RC3-
RD1+
RC1-
P100
TF05-51S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
OPC_OUT1
SDA
R159
100
R155
100
RCLK2+
C104
10pF
50V
READY
C105
10pF
50V
READY
RE2-
R104
22
R108
22
RB1-
R105
22
RD1+
R167
100
C108
100pF
50V
R165
100
RA2+
RCLK2-
R158
100
R156
100
BIT_SELECT
PWM_DIM
RC1+
RD1-
RB2-
/3D_FPGA_RESET
C106
10uF
16V
SCL
3V3
R161
22
R107
22
R102
22
RD2+
R164
100
C107
0.1uF
50V
12V_TCON
RA1+
R109
22
RC1-
RE1+
R157
100
OPC_OUT2
OPC_ENABLE
R162
100
R160
100
RD2-
RA1-
RC2+
RCLK1+
RE1-
R103
0
R100
4.7K
READY
R163
100
LVDS_SELECT
R106
22
R110
22
RA2-
RC2-
3D_POWER_EN
R166
100
RE2+
R101
4.7K
READY
RB1+
RB2+
RCLK1-
RCLK3+
R175
100
R179
100
RC4-
RE3+
R174
100
RB3-
P101
TF05-41S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
R178
100
RD4-
+12V_FORMATTER
RB4+
R173
100
RCLK3-
R177
100
RA3+
C111
100pF
50V
RCLK4+
RE3-
R172
100
RC3+
C109
10uF
16V
RE4+
RB4-
R171
100
RD3+
RA3-
C110
0.1uF
50V
RCLK4-
R170
100
RA4+
RC3-
RE4-
RC4+
R169
100
RD3-
R176
100
RB3+
RD4+
R168
100
RA4-
TDI
TDO
TCK
TMS
C120
0.1uF
16V
R123
22
R126
22
2V5
R125
22
R128
1K
R124
1K
R127
1K
P104
YFDW254-10S
1
2
3
4
5
6
7
8
9
10
R129
22
TDO
TDI
TMS
TCK
SYSCLK
CONFIG_DONE
MSEL[3]
MSEL[2]
MSEL[0]
/RESET2V5
MSEL[1]
R141
0
READY
R135
0
READY
MSEL[1]
R136
0
READY
R139
1K
MSEL[0]
MSEL[3]
R140
1K
R137
4.7K
AR100
22
2V5
MSEL[2]
TC1+
TA2-
TD1+
TB1+
TCLK1+
TD1-
TB1-
TA1+
TA1-
TA4+
TE2-
TB2-
TD2+
TB3+
TC1-
TCLK4-
TA3-
TC3-
TB2+
TE4+
TE3+
TD4+
TA3+
TCLK3+
TD2-
TE1+
TCLK2-
TCLK3-
TD3+
TE3-
TA2+
TE4-
TE2+
TA4-
TCLK4+
SDA2V5
TCLK2+
TB3-
TB4-
TC4-
TD3-
TCLK1-
TE1-
TB4+
TC4+
SCL2V5
TC2+
TC2-
TD4-
R150
22
OPT
D101
SAM2333
OPT
A2[RD]
C
A1[GN]
TP[3]
TA4+
TA3+
TD1+
TC1-
TA4-
C112
22uF
R154
22
OPT
TA3-
TB3-
TCLK2+
P102
TF05-51S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
TP[5]
TCLK1+
BIT_SELECT
TE1-
TA2-
R118
0
READY
TP[1]
TP[4]
TD2+
R115
22
D100
SAM2333
OPT
A2[RD]
C
A1[GN]
D102
SAM2333
OPT
A2[RD]
C
A1[GN]
TC4-
R114
22
TC2+
TA2+
OPC_OUT2
TE2-
OPC_ENABLE
C114
0.1uF
50V
TE2+
L100
CB3216PA501E
TCLK4+
R153
1K
OPT
LVDS_SELECT
R145
1K
OPT
TC4+
D103
SAM2333
OPT
A2[RD]
C
A1[GN]
R113
22
PWM_DIM
TCLK3-
TP[2]
TCLK2-
TD2-
R116
22
P103
TF05-41S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
TC1+
D105
SAM2333
OPT
A2[RD]
C
A1[GN]
TD3-
TE4-
TP[0]
TE4+
TB1-
TCLK4-
TB4+
TB2-
TA1-
TD4-
R111
22
TCLK1-
C113
10uF
16V
R144
22
OPT
R149
1K
OPT
TC3+
12V_TCON
R143
1K
OPT
D104
SAM2333
OPT
A2[RD]
C
A1[GN]
R151
1K
OPT
R180
0
READY
TA1+
R112
22
TC2-
R146
22
OPT
R148
22
OPT
TB4-
TC3-
TD1-
TB2+
TE3-
TD4+
OPC_OUT1
R147
1K
OPT
TE3+
TE1+
TB3+
TCLK3+
C115
100pF
50V
TD3+
R152
22
OPT
TB1+
TP[1]
TP[3]
TP[5]
TP[0]
TP[2]
TP[4]
IC100
EP3C55F484C8N
RXA0
N2
RXA0(N)
N1
RXA1
P2
RXA1(N)
P1
RXA2
R2
RXA2(N)
R1
RXA3
U2
RXA3(N)
U1
RXA4
V2
RXA4(N)
V1
RXACLK
T2
RXACLK(N)
T1
RXB0
B2
RXB0(N)
B1
RXB1
C2
RXB1(N)
C1
RXB2
F2
RXB2(N)
F1
RXB3
H2
RXB3(N)
H1
RXB4
J2
RXB4(N)
J1
RXBCLK
G2
RXBCLK(N)
G1
IC100
EP3C55F484C8N
NSTATUS
K6
NCONFIG
K5
CONFIG_DONE
M18
DCLK
K2
TCK
L2
TDO
L4
TMS
L1
TDI
L5
DATA0
K1
MSEL0
M17
MSEL1
L18
MSEL2
L17
MSEL3
K20
NCE
L3
ASDO
D1
NCSO
E2
SYSCLK54
G21
RST_N
G22
SCL
A3
SDA
B3
TEST7
J21
TEST6
J20
TEST5
J19
TEST4
J18
TEST3
H21
TEST2
H20
TEST1
H19
TEST0
H18
LED3
E21
LED2
E22
LED1
F19
LED0
F20
IC100
EP3C55F484C8N
NC_1
A11
NC_2
A12
NC_3
A20
NC_4
AA1
NC_5
AA2
NC_6
AA11
NC_7
AA12
NC_8
AA20
NC_9
AB5
NC_10
AB6
NC_11
AB11
NC_12
AB12
NC_13
B4
NC_14
B11
NC_15
B12
NC_16
B21
NC_17
B22
NC_18
C3
NC_19
C4
NC_20
C10
NC_21
C15
NC_22
C20
NC_23
C21
NC_24
C22
NC_25
D2
NC_26
D6
NC_27
D17
NC_28
D20
NC_29
D21
NC_30
D22
NC_31
E1
NC_32
E3
NC_33
E4
NC_34
E5
NC_35
E6
NC_36
E7
NC_37
E8
NC_38
E9
NC_39
E11
NC_40
E12
NC_41
E13
NC_42
E14
NC_43
E15
NC_44
F7
NC_45
F8
NC_46
F9
NC_47
F10
NC_48
F11
NC_49
F13
NC_50
F14
NC_51
F15
NC_52
F16
NC_53
F17
NC_54
F21
NC_55
F22
NC_56
G3
NC_57
G4
NC_58
G5
NC_59
G7
NC_60
G8
NC_61
G9
NC_62
G10
NC_63
G11
NC_64
G13
NC_65
G14
NC_66
G15
NC_67
G16
NC_68
G17
NC_69
G18
NC_70
H3
NC_71
H4
NC_72
H5
NC_73
H6
NC_74
H7
NC_75
H16
NC_76
H17
NC_77
J3
NC_78
J4
NC_79
J5
NC_80
J6
NC_81
J7
NC_82
J17
NC_83
K7
NC_84
K19
NC_85
L6
NC_86
M1
NC_87
M2
NC_88
M3
NC_89
M4
NC_90
M5
NC_91
M6
NC_92
N5
NC_93
N6
NC_94
N7
NC_95
N16
NC_96
N17
NC_97
P3
NC_98
P4
NC_99
P5
NC_100
P6
NC_101
P7
NC_102
P20
NC_103
R3
NC_104
R4
NC_105
R5
NC_106
R6
NC_107
R15
NC_108
T3
NC_109
T4
NC_110
T5
NC_111
T10
NC_112
T11
NC_113
T14
NC_114
T21
NC_115
T22
NC_116
U7
NC_117
U8
NC_118
U13
NC_119
U19
NC_120
V3
NC_121
V4
NC_122
V6
NC_123
V7
NC_124
W1
NC_125
W2
NC_126
Y1
NC_127
Y2
IC100
EP3C55F484C8N
LVDS_OUT_R1[9]
D13
LVDS_OUT_R1[8]
A10
LVDS_OUT_R1[7]
B10
LVDS_OUT_R1[6]
D10
LVDS_OUT_R1[5]
E10
LVDS_OUT_R1[4]
A9
LVDS_OUT_R1[3]
B9
LVDS_OUT_R1[2]
A8
LVDS_OUT_R1[1]
B8
LVDS_OUT_R1[0]
C8
LVDS_OUT_G1[9]
A16
LVDS_OUT_G1[8]
B16
LVDS_OUT_G1[7]
A15
LVDS_OUT_G1[6]
B15
LVDS_OUT_G1[5]
D15
LVDS_OUT_G1[4]
A14
LVDS_OUT_G1[3]
B14
LVDS_OUT_G1[2]
A13
LVDS_OUT_G1[1]
B13
LVDS_OUT_G1[0]
C13
LVDS_OUT_B1[9]
C19
LVDS_OUT_B1[8]
D19
LVDS_OUT_B1[7]
A18
LVDS_OUT_B1[6]
B18
LVDS_OUT_B1[5]
C18
LVDS_OUT_B1[4]
D18
LVDS_OUT_B1[3]
A17
LVDS_OUT_B1[2]
B17
LVDS_OUT_B1[1]
C17
LVDS_OUT_B1[0]
E16
LVDS_OUT_PIXCLK1
A4
LVDS_OUT_DE1
B20
LVDS_OUT_HS1
A19
LVDS_OUT_VS1
B19
GPIO_0
D8
GPIO_1
A7
GPIO_2
B7
GPIO_3
C7
GPIO_4
D7
GPIO_5
A6
GPIO_6
B6
GPIO_7
C6
GPIO_8
A5
GPIO_9
B5
LVDS_OUT_R2[9]
M20
LVDS_OUT_R2[8]
M21
LVDS_OUT_R2[7]
M22
LVDS_OUT_R2[6]
L21
LVDS_OUT_R2[5]
L22
LVDS_OUT_R2[4]
K17
LVDS_OUT_R2[3]
K18
LVDS_OUT_R2[2]
K21
LVDS_OUT_R2[1]
K22
LVDS_OUT_R2[0]
J22
LVDS_OUT_G2[9]
P17
LVDS_OUT_G2[8]
P21
LVDS_OUT_G2[7]
P22
LVDS_OUT_G2[6]
N18
LVDS_OUT_G2[5]
N19
LVDS_OUT_G2[4]
N20
LVDS_OUT_G2[3]
N21
LVDS_OUT_G2[2]
N22
LVDS_OUT_G2[1]
M16
LVDS_OUT_G2[0]
M19
LVDS_OUT_B2[9]
T17
LVDS_OUT_B2[8]
T18
LVDS_OUT_B2[7]
T19
LVDS_OUT_B2[6]
T20
LVDS_OUT_B2[5]
R17
LVDS_OUT_B2[4]
R18
LVDS_OUT_B2[3]
R19
LVDS_OUT_B2[2]
R20
LVDS_OUT_B2[1]
R21
LVDS_OUT_B2[0]
R22
LVDS_OUT_PIXCLK2
H22
LVDS_OUT_DE2
U20
LVDS_OUT_HS2
U22
LVDS_OUT_VS2
U21
GPIO_10
V21
GPIO_11
V22
GPIO_12
AA21
GPIO_13
W21
GPIO_14
W22
GPIO_15
AA22
GPIO_16
W20
GPIO_17
Y21
GPIO_18
W19
GPIO_19
Y22
TC3+
RCLK3+
RCLK3-
RCLK2-
RCLK2+
R138
4.7K
R142
0
READY
LVDS
2009/10/22
1     4
THE    SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS 
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE    SYMBOL MARK OF THE SCHEMETIC.
DDR_DQ[13]
SDDR_DQ[22]
DDR_DQ[24]
SDDR_DQ[11]
DDR_A[4]
DDR_DQ[11]
SDDR_DQ[27]
DDR_DQ[9]
SDDR_DQ[19]
DDR_DQ[5]
DDR_DQ[17]
DDR_DQ[4]
DDR_DQ[31]
DDR_DQ[31]
DDR_DQ[1]
DDR_DQ[27]
DDR_A[2]
SDDR_DQ[15]
DDR_DQ[7]
DDR_DQ[6]
DDR_DQ[8]
DDR_DQ[1]
SDDR_DQ[31]
DDR_DQ[19]
DDR_DQ[20]
DDR_DQ[13]
SDDR_DQ[29]
DDR_A[8]
DDR_A[9]
DDR_A[9]
DDR_A[11]
SDDR_DQ[2]
SDDR_DQ[23]
SDDR_DQ[14]
DDR_DQ[18]
DDR_DQ[14]
DDR_A[6]
SDDR_DQ[20]
DDR_DQ[3]
DDR_DQ[26]
SDDR_DQ[4]
DDR_DQ[15]
SDDR_DQ[3]
DDR_DQ[14]
DDR_DQ[12]
DDR_A[7]
DDR_A[12]
DDR_DQ[2]
DDR_A[10]
DDR_DQ[25]
DDR_DQ[28]
DDR_DQ[28]
DDR_DQ[22]
DDR_DQ[23]
SDDR_DQ[7]
DDR_DQ[4]
DDR_DQ[21]
DDR_DQ[0]
SDDR_DQ[9]
DDR_DQ[8]
SDDR_DQ[1]
DDR_DQ[24]
DDR_A[2]
DDR_DQ[19]
SDDR_DQ[12]
DDR_DQ[29]
DDR_DQ[16]
DDR_DQ[7]
DDR_DQ[30]
DDR_DQ[21]
DDR_A[5]
DDR_A[4]
SDDR_DQ[0]
DDR_DQ[15]
DDR_DQ[26]
DDR_DQ[23]
SDDR_DQ[6]
DDR_DQ[6]
DDR_DQ[10]
DDR_A[3]
SDDR_DQ[24]
SDDR_DQ[30]
DDR_DQ[27]
DDR_A[0]
DDR_A[8]
DDR_DQ[17]
DDR_A[11]
DDR_DQ[2]
DDR_DQ[29]
DDR_A[5]
DDR_A[6]
SDDR_DQ[18]
SDDR_DQ[13]
DDR_A[12]
DDR_A[0]
DDR_DQ[25]
SDDR_DQ[21]
DDR_A[1]
DDR_DQ[12]
DDR_A[7]
DDR_DQ[22]
DDR_DQ[10]
DDR_A[1]
DDR_DQ[11]
SDDR_DQ[25]
SDDR_DQ[8]
DDR_DQ[5]
DDR_DQ[16]
DDR_DQ[18]
SDDR_DQ[16]
SDDR_DQ[26]
DDR_DQ[0]
DDR_DQ[30]
SDDR_DQ[5]
SDDR_DQ[28]
DDR_A[10]
DDR_DQ[20]
DDR_DQ[3]
DDR_A[3]
DDR_DQ[9]
SDDR_DQ[10]
SDDR_DQ[17]
SDDR_DQ[14]
SDDR_DQ[9]
SDDR_DQ[8]
SDDR_DQ[15]
SDDR_DQ[12]
SDDR_DQ[13]
SDDR_DQ[10]
SDDR_DQ[11]
SDDR_DQ[4]
SDDR_DQ[1]
SDDR_DQ[3]
SDDR_DQ[7]
SDDR_DQ[2]
SDDR_DQ[0]
SDDR_DQ[5]
SDDR_DQ[6]
SDDR_DQ[20]
SDDR_DQ[22]
SDDR_DQ[19]
SDDR_DQ[17]
SDDR_DQ[21]
SDDR_DQ[18]
SDDR_DQ[23]
SDDR_DQ[16]
SDDR_DQ[27]
SDDR_DQ[25]
SDDR_DQ[26]
SDDR_DQ[30]
SDDR_DQ[28]
SDDR_DQ[31]
SDDR_DQ[29]
SDDR_DQ[24]
C237
0.1uF
16V
C407
0.1uF
16V
DDR_CKE
C256
0.1uF
16V
DDR_A[6]
DDR_A[7]
AR206
33
C286
0.1uF
16V
R203
1K
DDR_A[12-0]
C261
0.1uF
16V
C232
0.1uF
16V
C265
0.1uF
16V
DDR_BA[0]
2V5
DDR_LDQS[0]
DDR_A[8]
DDR_LDM[1]
C200
0.1uF
16V
C258
0.1uF
16V
C287
0.1uF
16V
C203
0.1uF
16V
R207
33
/DDR_CAS
AR211
56
C411
0.1uF
16V
1V2
AR214
56
DDR_BA[1]
DDR_CLK
C244
0.1uF
16V
1V8
C248
0.1uF
16V
C274
0.1uF
16V
1V8
AR213
56
C209
0.1uF
16V
DDR_A[6]
2V5
/DDR_RAS
DDR_A[5]
DDR_CLK
C249
0.1uF
16V
/DDR_CS
/DDR_CLK
C228
0.1uF
16V
1V2
C405
0.1uF
16V
C243
0.1uF
16V
DDR_CKE
DDR_ODT
C279
0.1uF
16V
C273
0.1uF
16V
R204
1K
1V8
C281
0.1uF
16V
AR202
33
R200
100
SDDR_DQ[31-16]
C213
0.1uF
16V
DDR_UDM[1]
C235
0.1uF
16V
SDDR_DQ[15-0]
/DDR_CS
C282
0.1uF
16V
DDR_ODT
DDR_A[12]
C239
0.1uF
16V
C260
0.1uF
16V
DDR_A[12-0]
DDR_A[4]
C215
0.1uF
16V
DDR_A[7]
DDR_LDQS[0]
C245
0.1uF
16V
AR201
33
/DDR_WE
R202
33
DDR_LDM[0]
DDR_UDQS[1]
DDR_CKE
DDR_A[8]
DDR_A[2]
/DDR_CS
AR215
56
1V8
R201
33
C409
0.1uF
16V
C214
10uF
16V
C275
0.1uF
16V
DDR_LDM[1]
DDR_A[9]
C229
0.1uF
16V
C259
0.1uF
16V
C292
0.1uF
16V
/DDR_CAS
AR212
56
R209
1K
R211
56
DDR_ODT
C208
0.1uF
16V
C223
0.1uF
16V
C284
0.1uF
16V
C403
0.1uF
16V
C227
0.1uF
16V
AR217
56
1V2
AR200
33
C268
0.1uF
16V
DDR_UDM[1]
2V5
C257
0.1uF
16V
DDR_A[8]
/DDR_WE
/DDR_CLK
DDR_LDQS[1]
AR209
56
C288
0.1uF
16V
C400
0.1uF
16V
C226
0.1uF
16V
2V5
C290
0.1uF
16V
R205
100
DDR_UDM[0]
DDR_A[11]
2V5
C298
0.1uF
16V
DDR_LDM[0]
DDR_UDM[0]
DDR_UDQS[0]
C404
10uF
16V
/DDR_RAS
IC200
H5PS5162FFR-S6C
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR_A[7]
SDDR_DQ[15-0]
C253
0.1uF
16V
DDR_CLK
DDR_A[0]
DDR_A[10]
C242
0.1uF
16V
AR207
33
DDR_VREF1
DDR_UDQS[0]
AR208
56
C272
0.1uF
16V
DDR_A[11]
DDR_BA[0]
DDR_A[2]
C204
470pF
50V
C221
0.1uF
16V
DDR_A[9]
DDR_A[12]
AR204
33
DDR_A[12]
C416
0.1uF
16V
C419
0.1uF
16V
DDR_A[5]
C212
0.1uF
16V
/DDR_CS
DDR_A[10]
DDR_CKE
AR216
56
/DDR_WE
IC201
H5PS5162FFR-S6C
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDR_A[2]
C234
0.1uF
16V
DDR_A[6]
/DDR_CAS
DDR_A[4]
C401
0.1uF
16V
/DDR_CAS
C241
0.1uF
16V
C271
0.1uF
16V
DDR_A[3]
C224
0.1uF
16V
C295
0.1uF
16V
C410
0.1uF
16V
C414
0.1uF
16V
C240
0.1uF
16V
AR205
33
C247
0.1uF
16V
C263
0.1uF
16V
1V8
C217
10uF
16V
DDR_BA[1]
DDR_BA[0]
DDR_LDQS[1]
1V8
DDR_BA[0]
C201
470pF
50V
/DDR_RAS
C289
0.1uF
16V
C420
0.1uF
16V
DDR_VTT
C276
0.1uF
16V
R206
33
C252
0.1uF
16V
C299
0.1uF
16V
C236
0.1uF
16V
C231
0.1uF
16V
C269
0.1uF
16V
C402
0.1uF
16V
DDR_A[9]
C255
0.1uF
16V
C225
0.1uF
16V
C264
0.1uF
16V
/DDR_WE
DDR_A[3]
C406
0.1uF
16V
DDR_A[1]
DDR_A[11]
DDR_VTT
C222
10uF
16V
C250
0.1uF
16V
C238
0.1uF
16V
AR210
56
DDR_VREF0
C246
0.1uF
16V
C266
0.1uF
16V
C293
0.1uF
16V
C206
0.1uF
16V
/DDR_CLK
C413
0.1uF
16V
1V2
DDR_BA[0]
C417
0.1uF
16V
DDR_A[4]
C230
0.1uF
16V
C280
0.1uF
16V
/DDR_CS
DDR_UDQS[1]
C294
0.1uF
16V
C233
0.1uF
16V
DDR_A[0]
DDR_A[0]
DDR_BA[1]
DDR_A[3]
/DDR_RAS
C415
0.1uF
16V
C216
100pF
50V
DDR_CKE
/DDR_CAS
/DDR_WE
C210
0.1uF
16V
C254
0.1uF
16V
DDR_A[1]
DDR_BA[1]
R210
56
C220
100pF
50V
R208
1K
C291
0.1uF
16V
DDR_BA[1]
C277
0.1uF
16V
C251
0.1uF
16V
C285
0.1uF
16V
C296
0.1uF
16V
C283
0.1uF
16V
C267
0.1uF
16V
/DDR_RAS
C262
0.1uF
16V
C218
0.1uF
16V
C297
0.1uF
16V
C421
0.1uF
16V
DDR_ODT
C202
100pF
50V
C412
0.1uF
16V
SDDR_DQ[31-16]
AR203
33
C278
0.1uF
16V
DDR_A[5]
DDR_VTT
DDR_ODT
C211
0.1uF
16V
C408
0.1uF
16V
DDR_A[1]
DDR_A[10]
C219
100pF
50V
C205
100pF
50V
C207
0.1uF
16V
C418
0.1uF
16V
C270
0.1uF
16V
IC100
EP3C55F484C8N
GND_1
L10
GND_2
L11
GND_3
M10
GND_4
M11
GND_5
L12
GND_6
L13
GND_7
M12
GND_8
M13
GND_9
N11
GND_10
K11
GND_11
N12
GND_12
K12
GND_13
K13
GND_14
N13
GND_15
N10
GND_16
K10
GND_17
J9
GND_18
F12
GND_19
H12
GND_20
H13
GND_21
J15
GND_22
K16
GND_23
L15
GND_24
N15
GND_25
R13
GND_26
R11
GND_27
R9
GND_28
P8
GND_29
H14
GND_30
H10
GND_31
H8
GND_32
N8
GND_33
R7
GND_34
T8
GND_35
T12
GND_36
P16
GND_37
L8
GND_38
M7
GND_39
A1
GND_40
C5
GND_41
C9
GND_42
C11
GND_43
C12
GND_44
C14
GND_45
C16
GND_46
A22
GND_47
E20
GND_48
G20
GND_49
L20
GND_50
P19
GND_51
V20
GND_52
Y20
GND_53
AB22
GND_54
Y18
GND_55
Y16
GND_56
Y12
GND_57
Y11
GND_58
Y9
GND_59
Y5
GND_60
AB1
GND_61
N3
GND_62
U3
GND_63
W3
GND_64
D3
GND_65
F3
GND_66
K3
GNDA1
U5
GNDA2
E18
GNDA3
F5
GNDA4
V18
IC100
EP3C55F484C8N
VCCA1
T6
VCCA2
F18
VCCA3
G6
VCCA4
U18
VCCD_PLL1
U6
VCCD_PLL2
E17
VCCD_PLL3
F6
VCCD_PLL4
V17
VCCIO1_1
D4
VCCIO1_2
F4
VCCIO1_3
K4
VCCIO2_1
N4
VCCIO2_2
U4
VCCIO2_3
W4
VCCIO3_1
AB2
VCCIO3_2
W5
VCCIO3_3
W9
VCCIO3_4
W11
VCCIO4_1
AB21
VCCIO4_2
W12
VCCIO4_3
W16
VCCIO4_4
W18
VCCIO5_1
P18
VCCIO5_2
V19
VCCIO5_3
Y19
VCCIO6_1
E19
VCCIO6_2
G19
VCCIO6_3
L19
VCCIO7_1
A21
VCCIO7_2
D12
VCCIO7_3
D14
VCCIO7_4
D16
VCCIO8_1
A2
VCCIO8_2
D5
VCCIO8_3
D9
VCCIO8_4
D11
VCCINT_1
J11
VCCINT_2
J12
VCCINT_3
L14
VCCINT_4
M14
VCCINT_5
P11
VCCINT_6
P12
VCCINT_7
L9
VCCINT_8
M9
VCCINT_9
J13
VCCINT_10
J14
VCCINT_11
K14
VCCINT_12
J10
VCCINT_13
K9
VCCINT_14
N9
VCCINT_15
P9
VCCINT_16
P10
VCCINT_17
P13
VCCINT_18
P14
VCCINT_19
N14
VCCINT_20
J16
VCCINT_21
K15
VCCINT_22
L16
VCCINT_23
M15
VCCINT_24
R12
VCCINT_25
R10
VCCINT_26
R8
VCCINT_27
H9
VCCINT_28
G12
VCCINT_29
J8
VCCINT_30
M8
VCCINT_31
T7
VCCINT_32
T9
VCCINT_33
T13
VCCINT_34
P15
VCCINT_35
H15
VCCINT_36
H11
VCCINT_37
K8
VCCINT_38
L7
DDR_VREF_1
AA18
DDR_VREF_2
AB4
DDR_VREF_3
U11
DDR_VREF_4
V9
DDR_VREF_5
V12
DDR_VREF_6
V16
IC100
EP3C55F484C8N
RAM_ADDR[12]
W10
RAM_ADDR[11]
Y15
RAM_ADDR[10]
AA6
RAM_ADDR[9]
U14
RAM_ADDR[8]
T16
RAM_ADDR[7]
AB10
RAM_ADDR[6]
R16
RAM_ADDR[5]
R14
RAM_ADDR[4]
Y17
RAM_ADDR[3]
U9
RAM_ADDR[2]
AB17
RAM_ADDR[1]
W14
RAM_ADDR[0]
AA17
RAM_LDQS_2
V10
RAM_LDQS_1
V13
RAM_UDQS_2
AB9
RAM_UDQS_1
Y13
RAM_CLK
U16
RAM_CLKN
U17
RAM_CKE
AA3
RAM_CSN
AB19
RAM_RASN
U15
RAM_CASN
Y14
RAM_WEN
Y4
RAM_BA[1]
AB3
RAM_BA[0]
Y6
RAM_ODT
AA19
RAM_LDM_2
V5
RAM_UDM_2
AA7
RAM_LDM_1
AA16
RAM_UDM_1
AA10
RAM_DATA[31]
AA9
RAM_DATA[30]
AA8
RAM_DATA[29]
V11
RAM_DATA[28]
AB8
RAM_DATA[27]
AB7
RAM_DATA[26]
U10
RAM_DATA[25]
Y8
RAM_DATA[24]
Y10
RAM_DATA[23]
V8
RAM_DATA[22]
W6
RAM_DATA[21]
W7
RAM_DATA[20]
Y3
RAM_DATA[19]
AA4
RAM_DATA[18]
Y7
RAM_DATA[17]
AA5
RAM_DATA[16]
W8
RAM_DATA[15]
AB14
RAM_DATA[14]
AA13
RAM_DATA[13]
AA15
RAM_DATA[12]
W13
RAM_DATA[11]
U12
RAM_DATA[10]
AB15
RAM_DATA[9]
AB13
RAM_DATA[8]
AA14
RAM_DATA[7]
T15
RAM_DATA[6]
W15
RAM_DATA[5]
AB20
RAM_DATA[4]
AB16
RAM_DATA[3]
V15
RAM_DATA[2]
AB18
RAM_DATA[1]
V14
RAM_DATA[0]
W17
DDR_VREF1
C422
0.1uF
16V
DDR_VREF0
C425
470pF
50V
C424
0.1uF
16V
C423
470pF
50V
2     3
2009/10/22
MEMORY
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