LG 47GA7900-UA (CHASSIS:LA37G) Service Manual ▷ View online
L9
LG1152D
LG1152D
AUD
BB_TP_DATA
DAC_DATA
AAD_DATA
HSR_P/M
CVBS
DIF(P/N)
SIF
Tuner
AV 1_Audio L/R
Comp 1_Audio L/R
A/V1
COMP1
A/V1_CVBS
Comp1 Y,Pb,Pr
HDMI
Switch
Switch
HDMI1~4
L9
LG1152A
LG1152A
USB1
USB2
USB3
USB
HUB
HUB
PHY
RMII
LAN
Qwerty - R
Q-Remote_R/TX
Audio
AMP
AMP
OPTIC
SPK
SPDIF
I2S
16
DDR
16
DDR
256MB×4
(1600)
(1600)
128MB×1
(1600)
(1600)
8
eMMC
8GB×1
Built-in WiFi
FRC
LG7303
LG7303
HS_LVDS
2Link
CHB_DATA
L9 Block diagram
ATSC Half NIM
DIF
SIF
Parallel TS
System
Demux
Demux
Audio DSP
Multi-STD
Audio Decoder
Multi-STD
Audio Decoder
BTSC AFE
10b@18.432MHz
w/ PLL
10b@18.432MHz
w/ PLL
1ch L/R
Audio-ADC
24b@48KHz
Audio-ADC
24b@48KHz
GBB AFE
1ch@30MHz
w/ PLL
1ch@30MHz
w/ PLL
Global Baseband
V/Q, DVB-T/C
V/Q, DVB-T/C
CVBS(6ch)
Component(2ch)
3ch Video
AFE
10b@165MHz
w/ LLPLL
AFE
10b@165MHz
w/ LLPLL
HDMI-Rx 1.4
(1-port PHY)
3D, 4kx2k
(1-port PHY)
3D, 4kx2k
HDMI(1ch)
Capture
Block
(3CH)
Block
(3CH)
AAD
(THAT)
(THAT)
Audio Codec1
(Digital Part)
(Digital Part)
Mux
Analog Chip
Digital Chip
Audio L/R (5-ch)
SW
I2S(stero)
Sound
DSP
DSP
I2S
SPDIF
Video Decoder
(
(
Dual HD
)
CVBS AFE(2-ch)
12b@54MHz
12b@54MHz
12 : CVBS
Mux
12
Diplay
Engine
Engine
MC NR,
Vertical MC IPC
Vertical MC IPC
Scaler, PE
OSD, VCR
OSD, VCR
LVDS
H.264 Encoder
SD upto 480p
SD upto 480p
12
PHY
(3-port)
(3-port)
USB2.0
Host (x3)
Host (x3)
DDR3-PHY
DDR3(x16) * 3
Ethernet
MAC
MAC
eMMC
Controller
Controller
CPU
Dual C-A9 (1GHz)
Graphic
Engine
2D-VG / 3D Open-ES2.0
Audio
10(data)+1(en)+5(gc)
4(val, err, clk, sop)
+8 (data)
+8 (data)
I2C
I2C
6(gbb, l9da)
I2C
Digital
Audio
Output
Audio
Output
LVDS
LVDS
Video
LVDS
Video
OSD
LVDS
Audio PLL
w/ DCO
w/ DCO
I2S (mono)
3(lrck, lrch, sck)
I2C
SW
SW
3D or UD
Data bridge
Data bridge
I2S or SPDIF
8
Audio Clocks
9
1ch mono
Audio-ADC
24b@48KHz
Audio-ADC
24b@48KHz
Audio Codec0
(Digital Part)
(Digital Part)
Mux
LVDS
interrupt
3(hdmi, 3ch, gbb)
3(lrck, lrch, sck)
Audio
HDMI
(1-Link)
(1-Link)
Tuner_CVBS
L9 Block diagram
CPU
xi_main
1 Ghz
DDR3PLL
xo_main
1.6Ghz
DDR3PLL1
1.6Ghz
24Mhz
DDR3PLL2
0
1
0
1
0
1
CT
R
R
1/2
1/5
1.6Ghz
1.6Ghz
Memory Controller
Memory Controller
Memory Controller
800Mhz
800Mhz
Video/Audio Block
CPU peripherial
CPU peripherial
dcoin_clk
DCO
DCO
200Mhz
200Mhz
Glitch-free logic
between
de_dco_out and
sdec_dco_out
de_dco_out and
sdec_dco_out
de_dco_out
sdec_dco_out
0
1
CT
R
R
DISPLL
u_DPLL
udnt_buf_dpll_fin
disp_fout
Clock Divide & Reset
generation w/ test logic
DE
TE
sclk
27Mhz
27Mhz
27Mhz
27Mhz
2 port USB PHY
1 port USB PHY
30/48Mhz
30/48 Mhz
i_core800_clk
i_core320_clk
i_m01_ddrclk
i_m2_ddrclk
u_crg
Clock Divide & Reset generation
w/ test logic
w/ test logic
Clock Divide & Reset generation
w/ test logic
w/ test logic
Clock Divide & Reset generation
w/ test logic
w/ test logic
Clock Divide & Reset generation
w/ test logic
w/ test logic
Clock Divide & Reset generation
w/ test logic
w/ test logic
USB controller
About 220 internally generated clocks
SSC setting
- 0xFD3001CC
- 0xFD3001D0
- 0xFD3001CC
- 0xFD3001D0
SSC setting
- 0xFD3001C4
- 0xFD3001D8
- 0xFD3001C4
- 0xFD3001D8
SSC setting
-0xFD300108
-0xFD30010C
-0xFD300108
-0xFD30010C
SSC setting
- 0xFD3001D4
- 0xFD3001D8
- 0xFD3001D4
- 0xFD3001D8
L9 Block diagram
ATSC H/NIM
Tuner
TDSS-H651F
I2C-CH6(Main)
IF_AGC
IF N/P
Main SoC
IFAGC
<ATSC>
ADC_I_INN/P
S
C
L/
D
A6
_3.3
_3.3
V
L9
(B1)
(B1)
/TU_RESET
TU_SIF
TU_CVBS
L9 Block diagram
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