DOWNLOAD LG 42LX6500-UB (CHASSIS:LA02R) Service Manual ↓ Size: 7.65 MB | Pages: 105 in PDF or view online for FREE

Model
42LX6500-UB (CHASSIS:LA02R)
Pages
105
Size
7.65 MB
Type
PDF
Document
Service Manual
Brand
Device
TV / LCD
File
42lx6500-ub-chassis-la02r.pdf
Date
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LG 42LX6500-UB (CHASSIS:LA02R) Service Manual ▷ View online

12. Wireless RX (Sink) 
HDMI
Connector
Control
Connector
SB9121
Network
Processor
SB9111
RF
Receiver
Embedded
CPU
SiI9134
HDMI
Transceiver
MX1605
Serial Flash
SPI Bus
D[35:0]
H/VSYNC
DE
IDCK
I2S(4line)
SPDIFO
I2C(2line)
DDC(2line)
TMDS(8line)
RST#
INT
INT
VCXO
VCXO
Video
PLL
Video
DAC
Audio
PLL
Audio
DAC
I2
C
I2C
ACLK
VCLK
Micom
RST#
CEC
ADCI_P/N
ADCQ_P/N
PCLK_P/N
DACI_P/N
DACQ_P/N
RF
Control
SLEEP
XTAL
(3.6864MHz)
OSC
(54MHz)
MCLK/SCK/W
S
I2C(2line)
13. 3D Formatter B/D
LG1120 (FRC)
S-Flash
(2MBIT)
DDR2 * 4
(512MBIT)
HW option
Dual Display
Control with
240Hz
(FRC)
TL2425MC(T-CON)
TL2425MC(T-CON)
LVDS_TX4(DATA[10]+CLK[2]
LVDS_TX3(DATA[10]+CLK[2]
LVDS_TX2(DATA[10]+CLK[2]
LVDS_TX1(DATA[10]+CLK[2]
LVDS_TX8(DATA[10]+CLK[2]
LVDS_TX7(DATA[10]+CLK[2]
LVDS_TX6(DATA[10]+CLK[2]
LVDS_TX5(DATA[10]+CLK[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
EEPROM
EEPROM
To panel
Left mini-LVDS signals (data[12]+clk[2]
Right mini-LVDS signals (data[12]+clk[2]
Left mini-LVDS signals (data[12]+clk[2]
Right mini-LVDS signals (data[12]+clk[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
FPGA
(EP3C55F484C6N)
DDR2 * 2
(512MBIT)
S-Flash
EPCS16SI8N
(2MBIT)
LVDS_TX4(DATA[10]+CLK[2]
LVDS_TX3(DATA[10]+CLK[2]
LVDS_TX2(DATA[10]+CLK[2]
LVDS_TX1(DATA[10]+CLK[2]
LVDS_TX8(DATA[10]+CLK[2]
LVDS_TX7(DATA[10]+CLK[2]
LVDS_TX6(DATA[10]+CLK[2]
LVDS_TX5(DATA[10]+CLK[2]
(960 X 1080 @ 240Hz)
(960 X 1080 @ 240Hz)
FRC
FRC
TCON
TCON
3DF
3DF
DTV Main Board
T-Con Board
240Hz
DTV 
SoC
DTV 
SoC
Spade
/Sparta
HDMI
Tuner
USB
PC In
Component
60Hz
240Hz
LVDS 2Ch
LVDS 8Ch
LVDS 8Ch
Active 240Hz LCD TV
Active 240Hz LCD TV
512Mb x 2
512Mb x 2
13-1. System Configuration : 3D LCD TV
3D Chip
Display Format
Input Format
R
L
R
Frame-by-Frame
L
R
L
R
HDMI 1.3
HDMI 1.4
Frame Packing
R
L
R
L
R
-IOP(M240)
-Edge(M240)
-IOP(M240)
-Edge(M240)
Module
3D Formatter In/Out type 
3D Formatter In/Out type 
FPGA
DDR2
H5PS5162FFR-S6C
32Mb x 16 x 2
FPGA
config.
Oscillator
LVDS Rx
(2 Ch)
LVDS Rx
(2 Ch)
LVDS Rx
(2 Ch)
LVDS Rx
(2 Ch)
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
3.3V 2.5V 1.8V 1.26V
LVDS
LVDS
FRC
240Hz
LVDS Rx
(2 Ch)
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
LVDS Tx
(2 Ch)
51P LVDS
LVDS, 
12V, I/F
Main 
Board
51P LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
TCON
240HZ
mini LVDS
mini LVDS
80P
mini LVDS
80P
mini LVDS
240Hz FRC + Formatter Board + TCON
Main Board I/F, I2C
12V
Power
Block
13-2. 240Hz + 3D Formatter + T-Con Block Diagram
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