LG 42LH40 (CHASSIS:LA92G) Service Manual ▷ View online
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
PV
LD1000
8.2K
R1015
0.1uF
16V
C1034
1K
R1063
47uF
16V
C1039
0.1uF
50V
C1003
OPT
R1067
KIA78R05F
IC1002
1
VIN
2
V C
3
V O
U T
4
N C
5
G N
D 1
6
G N
D 2
IF_AGC
+3.3V_PVSB
IF_P
TS_CLK
10uF
10V
C1011
IF_P
JP1006
33pF
C1006
FE_VMAIN
001:D24
82pF
50V
C1004
0.01uF
C1070
100uF
16V
C1002
470
PV
R1069
+3.3V_AVDD_PVSB
4.7K
R1001
IF_AGC
25MHz
X1005
2.2uF
16V
C1001
0.01uF
25V
C1008
POWER_EN
001:AR30;007:AH18
10K
R1000
0.1uF
50V
C1030
MLB-201209-0120P-N2
L1013
0
R1031
OPT
+3.3V_PVSB
FE_DEMOD_SDA
OPT
C1075
SC4215ISTRT
IC1000
3
VIN
2
EN
4
NC_2
1
NC_1
5
NC_3
6
VO
7
ADJ
8
GND
27pF 50V
OPT C1024
10uF
10V
C1051
OPT
0.047uF 50V
C1012
OPT
TS_VALID
VSB_RESET
100
R1028
OPT
0.1uF
50V
C1026
TS_VALID
270
R1020
220nH
L1011
10K
R1006
OPT
27pF
50V
OPT C1025
+1.2V_DVDD_PVSB
JP1005
BG2012B800
L1010
100uF
16V
C1018
+3.3V_FE
TS_SYNC
VCOMO
001:D24
0
R1005
FE_TUNER_SDA
0.1uF
C1068
FE_TUNER_SCL
500
L1006
OPT
+5V_TU
3216
10uF
16V
C1038
0.1uF
C1066
100
R1062
100pF 50V
C1015
1K
R1060
220nH
L1012
100uF
16V
C1035
TS_SYNC
SC156515M-1.8TR
IC1001
2
VIN
1
EN
3
GND
5
ADJ
4
VO
OPT
C1074
27pF
50V
C1071
TS_DATA[0-7]
+3.3V_DVDD_PVSB
0.1uF
50V
C1020
100
R1064
220uF
16V
C1054
OPT
100
AR1071
0.
1u
F
50V
C1014
0.01uF
50V
C1009
+1.2V_PVSB
FE_DEMOD_SCL
100
R1030
OPT
IF_N
22
R1023
JP1007
0.1uF
50V
C1021
OPT
+5V_TU
100uF
16V
C1077
0.1uF
50V
C1022
+3.3V_AVDD_PVSB
+3.3V_PVSB
CB3216PA501E
L1009
0.1uF
50V
C1033
0.1uF
16V
C1037
OPT
FE_TUNER_SDA
0
R1021
+3.3V_AVDD_PVSB
22
R1022
CB3216PA501E
L1007
+1.2V_PVSB
47
R1016
OPT
0
R1003
OPT
R1076
0.01uF
25V
C1041
+5V_EXT
0
R1026
1N4148W D1000
VSB_CTRL
22
R1077
LGDT3305
IC1004
1
NC_1
2
VINA2
3
VINA1
4
INCAP
5
VSSAAD10A
6
I2CSEL
7
ANTCON
8
VDD_1
9
I2CRPT_SCL
10
I2CRPT_SDA
11
IFOUT
12
RFOUT
13
TPERR
14
VDD33_1
15
TPVALID
16
TPDATA[0]
17
VSS33_1
18
TPDATA[1]
19
TPDATA[2]
20
TPDATA[3]
21
TPDATA[4]
22
TPDATA[5]
23
TPDATA[6]
24
TPDATA[7]
25TPCLK
26TPSOP
27NIRQ
28SDA
29VDD33_2
30SCL
31VSS_1
32VDD_2
33VSS_2
34VSS33_2
35PLLAVDD
36PLLAVSS
37
N R
S T
38
O P
M
39
VDD33_3
40
NC_2
41
VSS33_3
42
XTALI
43
X T
A LO
44
VSS_3
45
X M
46
VDD_3
47
VSSDAD10
48
V C
C A
A D
1 0A
100pF
50V
C1017
2.2uF
16V
C1000
5.1K
R1068
OPT
330nH
L1002
2.2K
R1004
OPT
OPT
R1066
47K
R1074
+5V_TU
36pF
50V
C1046
OPT
R1075
0.1uF
50V
C1007
SIFMO
001:W30
+12V
0.1uF
50V
C1044
TS_CLK
470
R1010
1/16W
100
AR1072
0.1uF
C1067
4.7K
R1013
+1.2V_DVDD_PVSB
0
R1032
0
5%
1/4W
R1034
36pF
50V
C1045
0
R1027
0.01uF
C1069
CM3216F100KE
10uH
L1001
3216
10uF
16V
C1028
FE_SIF
001:W30
0
R1065
JP1004
100
AR1070
27pF
50V
C1072
+5V_TU
220uF
16V
C1013
+5V_TU
+3.3V_DVDD_PVSB
15K
R1014
500
L1008
1uF
16V
OPT
C1010
0.1uF
50V
C1052
OPT
10K
R1008
500
L1005
OPT
0.1uF
50V
C1016
IF_N
+3.3V_DVDD_PVSB
10K
R1012
R1012
100
R1061
0
OPT
R1018
1M
R1072
12K
R1007
0.33uF
16V
C1036
0.1uF
50V
C1043
AS7809DTRE1
IC1003
2
GND
3
OUTPUT
1
INPUT
4.7K
R1017
0
R1033
1K
R1002
OPT
R1009
0.1uF
50V
C1032
270
R1019
FE_TUNER_SCL
0.1uF
16V
C1076
1uF
10V
C1073
0
R1073
OPT
+5V_TU
500
L1003
GND
0.01uF
25V
C1053
OPT
0.1uF
50V
C1005
CM2012F6R8KT
6.8uH
L1004
ISA1530AC1
Q1001
E
B
C
20K
R1011
R1011
22
R1078
0.1uF
C1040
100uF
16V
C1019
3216
10uF
16V
C1023
ISA1530AC1
Q1000
E
B
C
TDVW-H103F
TU1001
14
IF_AGC
13
DIF[-]
5
RF_AGC
12
DIF[+]
11
NC_3
2
NC_2
19
VIDEO
18
AUDIO
10
AS
4
+B1
1
NC_1
17
NC_4
9
CLOCK
8
DATA
3
GND_1
16
SIF
7
GND_2
6
NC[VT]
15
+B2
20
SHIELD
TS_DATA[0-7]
TS_DATA[0-7]
TS_DATA[2]
TS_DATA[7]
TS_DATA[4]
TS_DATA[6]
TS_DATA[0]
TS_DATA[5]
TS_DATA[1]
TS_DATA[3]
TPVALID
ANTCON
I2CRPT_SDA
MStar Application
VDD
VSS33
TPSOP
VCCAAD10A
V DD
JTAG
TPDATA[2]
VSSAAD10A
X M
SLIM_SCAN
TPCLK
TPDATA[4]
SDA
TPERR
TPDATA[3]
SCL
VSB +3.3V B+ BLOCK
PLLAVSS
VDD33
XTALI
I2CSEL
Option for FM Rejection
TPDATA[5]
NRST
TPDATA[7]
VSSAD10
The value of coil & cap’ could be changed to optimized each
VSS
VSS33
TPDATA[1]
VINA2
I2CRPT_SCL
PLLAVDD
MStar Application
Close to tuner
RF OUT
VDD33
MStar Application
VSS33
TPDATA[0]
VDD33
NIRQ
V0 = 0.8(R1+R2) / R2
R1
VSS
TPDATA[6]
(I2C Channel 6)
VDD
R2
IF OUT
VINA1
VROA
O PM
VSB +1.0V B+ BLOCK
VSS
INCAP
XTALO
TUNER
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
56
R41
1000pF
C18
56
R16
56
AR11
56
R42
0.
1u
F
C32
56
AR7
0.1uF
C40
56
R19
0.
1u
F
C9
56
R17
10uF
C30
33
R8
10uF
C23
0.
1u
F
C14
56
R18
0.
1u
F
C16
0.
1u
F
C29
+1.8V_S_DDR
56
R12
0.
1u
F
C27
56
R37
0.
1u
F
C19
56
R7
0.
1u
F
C38
56
AR4
56
AR13
+1.8V_S_DDR
1K
1 %
R47
0.
1u
F
C7
56
R33
0.
1u
F
C20
+1.8V_S_DDR
56
R28
1K
1 %
R4
56
R36
56
R38
150
OPT
R2
0.
1u
F
C25
0.
1u
F
C17
56
R43
56
R6
33
R31
10uF
C3
0.1uF
C22
56
R30
0.
1u
F
C11
0.
1u
F
C41
0.
1u
F
C34
HYB18TC512160B2F-2.5
IC1
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
56
R10
33
R32
0.
1u
F
C36
HYB18TC512160B2F-2.5
IC2
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
56
R14
1000pF
C2
0.
1u
F
C6
56
R11
0.
1u
F
C10
56
R35
+1.8V_DDR
0.
1u
F
C5
56
R13
56
AR2
0.
1u
F
C43
10uF
C13
56
AR9
56
R29
150
OPT
R45
56
AR3
0.
1u
F
C35
56
R40
0.
1u
F
C33
BLM18PG121SN1D
L1
1K1
%
R5
+1.8V_S_DDR
+1.8V_S_DDR
56
R39
56
AR5
1000pF
C42
56
R15
56
R20
0.
1u
F
C8
56
R22
56
R34
0.1uF
C1
0.
1u
F
C15
+1.8V_S_DDR
56
R27
56
AR14
56
AR12
56
AR1
56
AR8
56
R21
56
AR6
1K
1 %
R44
0.
1u
F
C12
33
R9
+1.8V_S_DDR
1K
1 %
R23
0.
1u
F
C24
56
AR10
+1.8V_S_DDR
1K
1 %
R24
0.
1u
F
C37
0.
1u
F
C31
0.
1u
F
C4
0.
1u
F
C21
0.
1u
F
C39
MSD3159GV
IC100
B_DDR2_A0
T26
B_DDR2_A1
AF26
B_DDR2_A2
T25
B_DDR2_A3
AF23
B_DDR2_A4
T24
B_DDR2_A5
AE23
B_DDR2_A6
R26
B_DDR2_A7
AD22
B_DDR2_A8
R25
B_DDR2_A9
AC22
B_DDR2_A10
AD23
B_DDR2_A11
R24
B_DDR2_A12
AE22
B_DDR2_BA0
AC23
B_DDR2_BA1
AC24
B_DDR2_BA2
AB22
B_DDR2_MCLK
V25
/B_DDR2_MCLK
V24
B_DDR2_CKE
AB23
B_DDR2_ODT
U26
/B_DDR2_RAS
U25
/B_DDR2_CAS
U24
/B_DDR2_WE
AB24
B_DDR2_DQS0
AB26
B_DDR2_DQS1
AA26
B_DDR2_DQM0
AC25
B_DDR2_DQM1
AC26
B_DDR2_DQSB0
AB25
B_DDR2_DQSB1
AA25
B_DDR2_DQ0
W25
B_DDR2_DQ1
AE26
B_DDR2_DQ2
W24
B_DDR2_DQ3
AF24
B_DDR2_DQ4
AF25
B_DDR2_DQ5
V26
B_DDR2_DQ6
AE25
B_DDR2_DQ7
W26
B_DDR2_DQ8
Y26
B_DDR2_DQ9
AD25
B_DDR2_DQ10
Y25
B_DDR2_DQ11
AE24
B_DDR2_DQ12
AD26
B_DDR2_DQ13
Y24
B_DDR2_DQ14
AD24
B_DDR2_DQ15
AA24
A_MVREF
D15
A_DDR2_A0
C13
A_DDR2_A1
A22
A_DDR2_A2
B13
A_DDR2_A3
C22
A_DDR2_A4
A13
A_DDR2_A5
A23
A_DDR2_A6
C12
A_DDR2_A7
B23
A_DDR2_A8
B12
A_DDR2_A9
C23
A_DDR2_A10
B22
A_DDR2_A11
A12
A_DDR2_A12
A24
A_DDR2_BA0
C24
A_DDR2_BA1
B24
A_DDR2_BA2
D24
A_DDR2_MCLK
B14
/A_DDR2_MCLK
A14
A_DDR2_CKE
D23
A_DDR2_ODT
D14
/A_DDR2_RAS
D13
/A_DDR2_CAS
D12
/A_DDR2_WE
D22
A_DDR2_DQS0
B18
A_DDR2_DQS1
C17
A_DDR2_DQM0
C18
A_DDR2_DQM1
A19
A_DDR2_DQSB0
A18
A_DDR2_DQSB1
B17
A_DDR2_DQ0
B15
A_DDR2_DQ1
A21
A_DDR2_DQ2
A15
A_DDR2_DQ3
B21
A_DDR2_DQ4
C21
A_DDR2_DQ5
C14
A_DDR2_DQ6
C20
A_DDR2_DQ7
C15
A_DDR2_DQ8
C16
A_DDR2_DQ9
C19
A_DDR2_DQ10
B16
A_DDR2_DQ11
B20
A_DDR2_DQ12
A20
A_DDR2_DQ13
A16
A_DDR2_DQ14
B19
A_DDR2_DQ15
A17
BDDR2_A[9]
BDDR2_A[1]
BDDR2_CKE
ADDR2_DQS1_N
SDDR_D[3]
SDDR_D[10]
SDDR_A[2]
TDDR_A[0]
SDDR_A[11]
SDDR_DQS1_N
BDDR2_DQS0_P
BDDR2_A[0]
ADDR2_ODT
ADDR2_A[6]
SDDR_BA[0]
TDDR_D[11]
TDDR_D[1]
ADDR2_CKE
ADDR2_A[0]
SDDR_A[5]
ADDR2_D[5]
ADDR2_D[1]
TDDR_D[13]
TDDR_D[6]
SDDR_A[10]
BDDR2_A[10]
ADDR2_A[2]
SDDR_A[9]
BDDR2_MCLK
TDDR_A[1]
ADDR2_A[1]
BDDR2_D[9]
BDDR2_A[4]
BDDR2_DQM0_P
BDDR2_D[0-15]
TDDR_A[0]
BDDR2_A[10]
TDDR_D[15]
ADDR2_D[15]
ADDR2_D[7]
TDDR_DQM0_P
TDDR_DQS1_P
SDDR_A[0]
TDDR_D[5]
TDDR_D[11]
TDDR_D[4]
SDDR_D[13]
TDDR_A[5]
BDDR2_A[7]
BDDR2_D[5]
BDDR2_ODT
ADDR2_A[7]
TDDR_D[4]
TDDR_A[11]
SDDR_D[8]
TDDR_A[10]
ADDR2_A[12]
TDDR_CKE
SDDR_D[4]
ADDR2_BA[0]
TDDR_A[8]
ADDR2_D[3]
ADDR2_D[7]
TDDR_D[7]
/BDDR2_CAS
TDDR_D[8]
BDDR2_D[13]
ADDR2_D[6]
TDDR_DQS0_N
BDDR2_D[3]
SDDR_DQM0_P
SDDR_D[2]
/TDDR_CAS
BDDR2_D[10]
ADDR2_A[5]
ADDR2_A[5]
TDDR_D[1]
SDDR_D[11]
TDDR_A[9]
/TDDR_RAS
BDDR2_D[1]
BDDR2_A[11]
TDDR_A[4]
BDDR2_D[2]
SDDR_D[6]
ADDR2_D[8]
TDDR_A[8]
SDDR_A[6]
BDDR2_D[12]
SDDR_A[1]
BDDR2_A[0]
TDDR_D[0]
TDDR_D[12]
BDDR2_D[15]
TDDR_D[6]
SDDR_D[1]
TDDR_D[12]
/SDDR_CAS
BDDR2_A[1]
SDDR_DQM1_P
ADDR2_A[4]
ADDR2_A[11]
TDDR_A[7]
BDDR2_D[0]
TDDR_D[14]
TDDR_A[2]
SDDR_D[7]
BDDR2_A[2]
TDDR_A[6]
BDDR2_A[11]
ADDR2_D[14]
BDDR2_D[15]
ADDR2_D[10]
BDDR2_A[8]
SDDR_A[4]
SDDR_A[12]
SDDR_D[10]
SDDR_D[14]
BDDR2_D[12]
SDDR_A[3]
ADDR2_DQS0_P
TDDR_DQM1_P
BDDR2_D[9]
TDDR_A[0-12]
BDDR2_D[6]
TDDR_A[5]
ADDR2_D[12]
BDDR2_A[6]
ADDR2_A[9]
BDDR2_D[3]
SDDR_A[11]
TDDR_BA[1]
SDDR_D[14]
ADDR2_A[0]
SDDR_A[8]
SDDR_ODT
TDDR_D[14]
ADDR2_A[9]
TDDR_D[2]
BDDR2_D[13]
ADDR2_D[13]
ADDR2_D[6]
ADDR2_D[14]
SDDR_D[12]
ADDR2_D[1]
ADDR2_A[6]
TDDR_D[3]
BDDR2_D[2]
BDDR2_D[10]
ADDR2_BA[1]
BDDR2_A[8]
ADDR2_A[12]
BDDR2_A[2]
BDDR2_A[5]
SDDR_A[7]
SDDR_D[7]
/SDDR_RAS
TDDR_D[0]
ADDR2_D[2]
TDDR_A[3]
/ADDR2_RAS
SDDR_A[8]
SDDR_D[9]
SDDR_D[5]
/ADDR2_WE
BDDR2_D[5]
BDDR2_D[6]
ADDR2_D[15]
SDDR_BA[1]
SDDR_A[0]
SDDR_D[1]
SDDR_CKE
ADDR2_D[3]
SDDR_D[0]
ADDR2_D[9]
TDDR_A[6]
TDDR_A[12]
BDDR2_D[4]
TDDR_A[4]
SDDR_A[10]
/TDDR_MCLK
ADDR2_D[12]
BDDR2_D[7]
TDDR_D[9]
SDDR_D[15]
ADDR2_D[10]
ADDR2_MCLK
TDDR_A[9]
SDDR_D[4]
SDDR_DQS0_N
BDDR2_A[12]
ADDR2_D[0]
SDDR_D[0]
TDDR_D[3]
SDDR_A[7]
SDDR_D[13]
SDDR_D[0-15]
SDDR_A[3]
ADDR2_A[11]
ADDR2_D[2]
TDDR_A[11]
TDDR_D[13]
ADDR2_A[8]
TDDR_D[5]
ADDR2_DQM0_P
BDDR2_A[12]
ADDR2_A[1]
TDDR_D[8]
BDDR2_BA[0]
BDDR2_D[11]
BDDR2_A[9]
/ADDR2_CAS
BDDR2_D[14]
BDDR2_D[14]
BDDR2_DQM1_P
SDDR_CK
ADDR2_A[8]
ADDR2_D[5]
SDDR_A[12]
ADDR2_A[0-12]
ADDR2_D[9]
SDDR_D[6]
BDDR2_DQS1_N
ADDR2_D[11]
ADDR2_A[7]
TDDR_DQS0_P
SDDR_A[1]
BDDR2_DQS1_P
SDDR_DQS1_P
SDDR_D[3]
ADDR2_A[10]
SDDR_D[5]
ADDR2_D[0-15]
TDDR_DQS1_N
SDDR_D[8]
SDDR_D[9]
TDDR_A[2]
ADDR2_A[4]
TDDR_D[10]
ADDR2_D[4]
SDDR_D[12]
SDDR_A[9]
SDDR_D[15]
TDDR_A[12]
TDDR_D[9]
TDDR_D[0-15]
BDDR2_D[4]
SDDR_A[0-12]
BDDR2_A[3]
SDDR_D[11]
SDDR_A[6]
ADDR2_A[10]
TDDR_D[2]
ADDR2_DQM1_P
SDDR_A[4]
/BDDR2_WE
ADDR2_D[8]
TDDR_BA[0]
BDDR2_A[0-12]
BDDR2_D[1]
BDDR2_BA[1]
ADDR2_D[11]
TDDR_D[10]
/BDDR2_RAS
ADDR2_A[3]
BDDR2_A[6]
TDDR_A[7]
TDDR_A[3]
BDDR2_D[8]
TDDR_A[10]
TDDR_A[1]
TDDR_D[15]
BDDR2_D[0]
BDDR2_A[4]
BDDR2_D[8]
ADDR2_DQS1_P
ADDR2_D[13]
/BDDR2_MCLK
/ADDR2_MCLK
SDDR_A[2]
BDDR2_A[7]
ADDR2_DQS0_N
/SDDR_WE
TDDR_D[7]
ADDR2_A[3]
SDDR_DQS0_P
SDDR_D[2]
ADDR2_D[4]
/TDDR_WE
ADDR2_D[0]
/SDDR_CK
BDDR2_D[11]
TDDR_MCLK
BDDR2_A[3]
SDDR_A[5]
BDDR2_DQS0_N
BDDR2_D[7]
ADDR2_A[2]
BDDR2_A[5]
DDR2 1.8V By CAP - Place these Caps near Memory
DDR2
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
0.
1u
F
C1146
DPM
13:U20;13:AI20
SOE_L
13:G21
56
R1151
URSA_DQSB3
12:Q11
R M
L V
2 N
13:M18
M E
M C
_ R
X E
3 -
1:R38
M_SPI_CK
AZ27
RK7002T116
Q1100
S
D
G
+3.3V
220
R1141
LMLV5N
13:G19
URSA_BA0
12
:T
9;
12
:V
10
0.
1u
F
C1127
H_CONV
13:G21;13:M21
1KOPT
R1135
GSC
13:G22;13:M21
M E
M C
_ R
X O
4 +
1:R35
10uF
C1115
MEMC_SDA
L31
1K
R1136
0.1uF
C1119
0.1uF
C1152
LED_LCM_FRC
AJ21
LMLV1P
13:G17
100
R1110
M_XTALI
008:P27
U R
S A
_ D
Q M
1
12:Y12
OPT_P
13:M16
33
R1106
R M
L V
7 N
13:M20
URSA_DQS3
12:Q12
1K
R1134
120-ohm
L1103
FLK
13:U20
R M
L V
7 P
13:M19
LMCLKN
13:G19
M_SPI_DI
AZ26
33
R1126
M E
M C
_ R
X E
4 -
1:R37
100
R1117
1K
M+S_47
R1161
0.
1u
F
C1162
0.
1u
F
C1161
+3.3V_MEMC
RMLV8N
13:M20
0.1uF
C1165
22uF
C1100
SOE
AJ24
URSA_DQM2
12:Q12
10pF
50V
OPT
C1120
+3.3V_ST
URSA_DQS0
12:Y12
R M
L V
6 N
13:M19
1K
R1100
M E
M C
_ R
X O
4 -
1:R35
0.
1u
F
C1109
33
R1130
+3.3V_MEMC
10K
R1158
W25X20AVSNIG
IC1101
3
WP
2
DO
4
GND
1
CS
5
DIO
6
CLK
7
HOLD
8
VCC
R M
L V
0 P
13:M17
R M
L V
5 N
13:M19
+3.3V_MEMC
0.
1u
F
C1131
GSP_R
13:G22;13:M21
10uF
C1149
+3.3V_MEMC
MEMC_SDA
1:AI7
100
R1114
R M
L V
2 P
13:M17
100
R1120
33
R1159
100
R1111
U R
S A
_ M
C LK
1
12:Y15
10pF
50V
OPT
C1124
0.
1u
F
C1151
M E
M C
_ R
X O
3 +
1:R35
R M
L V
1 P
13:M17
M_SPI_DO
AS27
0.
1u
F
C1103
U R
S A
_ D
Q M
0
12:Y12
10pF
50V
OPT
C1122
JTP-1127WEM
SW1100
12
4
3
0
R1156
33
R1132
OPT
10pF
50V
OPT
C1125
R M
L V
6 P
13:M19
M_XTALI
AV33
120-ohm
L1104
0.
1u
F
C1128
0.
1u
F
C1108
10K
R1144
M E
M C
_ R
X E
1 -
1:R39
FRC_DQ[0-31]
12:E20;12:AL20
0.1uF
C1138
RMLV8P
13:M20
WP_FLASH_FRC
AJ21
LMLV0N
13:G17
U R
S A
_ W
E Z
12
:T
9;
12
:V
10
LMCLKP
13:G19
SOE_R
13:M20
POL
13:G21;13:M21
SOE
AR15
M E
M C
_ R
X E
0 -
1:R39
10uF
C1117
10pF
50V
OPT
C1123
0.1uF
C1142
+1.8V_MEMC
1N4148W
100V
D1100
LMLV3P
13:G18
LMLV0P
13:G17
100
R1118
M E
M C
_ R
X E
3 +
1:R38
56
R1138
10uF
C1116
0.
1u
F
C1147
URSA_A[0-12]
12:V19
M E
M C
_ R
X O
0 +
1:R36
URSA_DQM3
12:Q12
0.1uF
C1135
M E
M C
_ R
X E
2 -
1:R38
10uF
C1148
R M
L V
3 P
13:M18
33
R1127
100
R1124
1K
M+S_42
R1163
1uF
C1136
0.1uF
C1154
56
R1166
OPT
0.
1u
F
C1132
OPT_N
13:G17;13:M16
M _X
T A
L O
AR33
120-ohm
L1101
150
R1140
M E
M C
_ R
X E
2 +
1:R38
M E
M C
_ R
X O
C -
1:R34
URSA_MCLK
12:Q15
LMLV8P
13:G20
+3.3V_MEMC
15pF
C1155
100
R1150
100
R1115
56
R1152
LMLV3N
13:G18
0.
1u
F
C1134
100
R1112
0.1uF
C1157
M E
M C
_ R
X O
0 -
1:R36
M E
M C
_ R
X O
C +
1:R34
LED_LCM_FRC
AS20
0.
1u
F
C1110
1K
OPT
R1101
22uF
C1144
URSA_ODT
12:Q14;12:Y14
M E
M C
_ R
X E
C +
1:R37
MEMC_SCL
AJ21
MEMC_SCL
1:AI7
M E
M C
_ R
X O
2 -
1:R35
10uF
C1145
+3.3V_MEMC
M_XTALO
008:P27
MEMC_RESET
1:AB21
0.
1u
F
C1130
M E
M C
_ R
X O
1 -
1:R36
100
R1116
R M
L V
5 P
13:M19
R M
L V
0 N
13:M17
GSP
13:G21;13:M21
15pF
C1156
0.
1u
F
C1129
+5V_GENERAL
URSA_DQSB2
12:Q11
0.
1u
F
C1111
+3.3V_MEMC
LMLV6P
13:G19
GOE
13:G22;13:M22
120-ohm
L1105
10uF
C1105
M_SPI_DI
AJ20
LMLV6N
13:G20
WP_FLASH_FRC
13:G21;13:M21
1M
R1142
1KOPT
R1137
0
R1154
1K
R1162
M+S_47
0.
1u
F
C1163
10pF
50V
C1160
OPT
0.1uF
C1164
0.1uF
C1166
URSA_RASZ
12
:S
16
;1
2:
W1
6
+3.3V_MEMC
M E
M C
_ R
X O
3 -
1:R35
1K
M+S_42
R1160
33
R1129
URSA_DQS1
12:Y12
M E
M C
_ R
X E
0 +
1:R39
10K
R1125
OPT
820
R1123
0.1uF
C1114
LMLV2P
13:G18
M_SPI_CZ
AS28
M_SPI_DO
AJ20
33
R1108
OPT
M_SPI_CZ
AJ21
10uF
C1106
0.
1u
F
C1102
4.7K
R1165
120-ohm
L1102
10pF
50V
OPT
C1121
4.7K
R1153
10uF
C1101
100
R1113
M E
M C
_ R
X E
4 +
1:R38
1uF
C1113
10pF
OPT
C1210
0
R1155
0
R1157
R M
L V
1 N
13:M17
M_SPI_CK
AJ20
BL-HB533A-AV-TRB
LD1100
0.1uF
C1139
URSA_DQSB1
12:Y11
0.
1u
F
C1112
M E
M C
_ R
X E
C -
1:R37
URSA_DQSB0
12:Y11
URSA_DQS2
12:Q12
10K
R1103
0.1uF
C1153
33
R1131
U R
S A
_ M
C L
K Z
1
12:Y14
URSA_BA1
12
:T
9;
12
:V
10
U R
S A
_ M
C LK
E
12
:T
9;
12
:V
10
10uF
C1133
R M
C LK
P
13:M18
+3.3V_MEMC
LMLV7P
13:G20
100
R1119
LMLV2N
13:G18
0.
1u
F
C1104
100
R1109
R M
L V
3 N
13:M18
10pF
50V
C1159
0.1uF
C1118
0
OPT
R1133
M E
M C
_ R
X E
1 +
1:R39
120-ohm
L1100
R M
C LK
N
13:M18
0.
1u
F
C1150
LMLV1N
13:G18
LMLV5P
13:G19
M E
M C
_ R
X O
1 +
1:R36
M E
M C
_ R
X O
2 +
1:R36
33pF
C1158
+1.26V_MEMC
33
R1107
12MHz
X1100
120-ohm
L1106
0.1uF
C1137
33
R1128
LMLV7N
13:G20
56
R1139
10K
R1102
TJC2508-4A
P1100
1
2
3
4
0.1uF
C1140
URSA_CASZ
12
:S
16
;1
2:
W1
6
LMLV8N
13:G20
0.1uF
C1141
URSA_MCLKZ
12:Q14
LGE7327N [ MST7327N(FRC Tcon) ]
IC1100
SDAS
E1
SCLS
D1
GPIO[8]
F1
GPIO[9]
G1
GND_14
K8
VDDC_1
E5
GPIO[10]
E2
GPIO[11]
F2
GPIO[12]
F3
GPIO[13]
G2
GPIO[22]
M4
GPIO[23]
M5
GPIO[14]
G3
GPIO[15]
E4
GPIO[16]
F4
GPIO[17]
G4
GPIO[18]
H4
GPIO[19]
J4
GPIO[20]
K4
GPIO[21]
L4
VDDP_2
J6
GND_7
H9
GND_15
K9
VDDC_2
F6
MDATA[20]
H1
MDATA[19]
H2
MDATA[17]
H3
MDATA[22]
J1
MDATA[27]
J2
MDATA[28]
J3
MDATA[25]
K1
MDATA[30]
K2
AVDD_DDR_2
K6
DDR2_DQM[3]
K3
DDR2_DQM[2]
L1
GND_10
J8
DDR2_DQS[2]
L2
DDR2_DQSB[2]
L3
AVDD_DDR_4
L6
VDDP_3
L8
GND_8
H10
DDR2_DQS[3]
M1
DDR2_DQSB[3]
M2
AVDD_DDR_5
L7
MDATA[31]
M3
MDATA[24]
N1
GND_11
J9
MDATA[26]
N2
MDATA[29]
N3
AVDD_DDR_6
L10
MDATA[23]
P1
MDATA[16]
R1
MDATA[18]
T1
MDATA[21]
T2
MCLK[0]
R2
MCLKZ[0]
P2
GND_1
G7
AVDD_MEMPLL
L9
MVREF
N5
ODT
N4
R A
S Z
T3
C A
S Z
R3
MADR[0]
P3
MADR[2]
T4
MADR[4]
R4
GND_12
J1
0
MADR[6]
P4
MADR[8]
T5
MADR[11]
R5
W E
Z
P5
BADR[1]
T6
BADR[0]
R6
MADR[1]
P6
MADR[10]
T7
A V
D D
_ D
D R
_ 7
L11
MADR[5]
R7
MADR[9]
P7
MADR[12]
T8
MADR[7]
R8
MADR[3]
P8
M C
L K
E
N8
GND_16
K10
V D
D C
_ 3
F7
MDATA[4]
T9
MDATA[3]
R9
GND_13
K7
MDATA[1]
P9
MDATA[6]
T10
A V
D D
_ D
D R
_ 3
K11
MDATA[11]
R10
MDATA[12]
P10
MDATA[9]
T11
MDATA[14]
R11
A V
D D
_ D
D R
_ 1
J1
1
DDR2_DQM[1]
P11
DDR2_DQM[0]
T12
DDR2_DQS[0]
R12
DDR2_DQSB[0]
P12
GND_9
J7
VDDP_1
H11
DDR2_DQS[1]
T13
DDR2_DQSB[1]
R13
MDATA[15]
P13
MDATA[8]
T14
MDATA[10]
R14
MDATA[13]
P14
MDATA[7]
T15
MDATA[0]
R15
MDATA[2]
P15
MDATA[5]
T16
MCLK[1]
R16
MCLKZ[1]
P16
GPIO[26]
N9
GPIO[27]
N10
GND_17
N11
RESET
M11
V D
D C
_ 4
G6
GPIO_3
D8
GPIO_5
D10
GPIO_9
E10
GPIO_8
E3
GPIO_1
D2
LAV8P
C15
LAV8N
B15
WPWM
A15
OPTP
A16
OPTN
B16
FLK
C16
GCLK6
D15
GCLK5
D16
AVDD_33_2
F9
GND_4
G10
LBV0P
E15
LBV0N
E16
LBV1P
E14
LBV1N
F14
LBV2P
F16
LBV2N
F15
LBV3P
G15
LBV3N
G16
LBVCKP
G14
LBVCKN
H14
LBV5P
H16
LBV5N
H15
LBV6P
J15
LBV6N
J16
LBV7P
J14
LBV7N
K14
GND_3
G9
LBV8P
L14
LBV8N
L15
GOE
L16
GSC
M16
AVDD_33_1
F8
GSPR
M15
GSP
M14
SOE
N16
POL
N15
VDDC_5
H6
GPIO[24]
N6
GPIO[7]
E12
GPIO[6]
D14
GPIO[5]
F12
GPIO[4]
E13
HCONV
F13
SPM
G13
LEDON
H13
GPIO[0]
J13
PWM0
K12
PWM1
L12
CSZ
K13
SDO
M12
SDI
M13
SCK
L13
GPIO[30]
N14
GPIO[29]
N13
GPIO[28]
N12
RE4P
B1
RE4N
A1
RE3P
C1
RE3N
C2
R E
C K
P
A2
R E
C K
N
B2
RE2P
B3
RE2N
A3
RE1P
C3
RE1N
C4
RE0P
A4
RE0N
B4
AVDD_LVDS_1
F11
GND_6
H8
RO4P
B5
R O
4 N
A5
RO3P
C5
R O
3 N
C6
R O
C K
P
A6
R O
C K
N
B6
RO2P
B7
R O
2 N
A7
RO1P
C7
R O
1 N
C8
RO0P
A8
R O
0 N
B8
AVDD_LVDS_2
G11
GND_5
H7
S C
A N
_ B
L K
K15
SCAN_BLK1
K16
X O
U T
D4
XIN
D3
V D
D _E
V E
N
B14
V D
D _O
D D
A14
S D
A M
D5
S C
L M
D6
GPIO[25]
N7
GPIO_10
E11
GPIO_7
D13
GPIO_6
D11
GND_2
G8
A V
D D
_ P
L L
F10
LAV0P
B9
L A
V 0N
A9
LAV1P
C9
L A
V 1N
C10
LAV2P
A10
L A
V 2N
B10
LAV3P
B11
L A
V 3N
A11
L A
V C
K P
C11
L A
V C
K N
C12
LAV5P
A12
L A
V 5N
B12
GPIO_4
D9
GPIO_2
D7
LAV6P
B13
L A
V 6N
A13
LAV7P
C13
L A
V 7N
C14
R E
X T
D12
FRC_DQ[14]
FRC_DQ[1]
FRC_DQ[20]
FRC_DQ[5]
FRC_DQ[0-31]
FRC_DQ[0]
URSA_A[12]
FRC_DQ[29]
FRC_DQ[16]
FRC_DQ[30]
FRC_DQ[25]
URSA_A[6]
URSA_A[8]
FRC_DQ[27]
URSA_A[11]
URSA_A[9]
URSA_A[0]
URSA_A[1]
FRC_DQ[3]
FRC_DQ[10]
FRC_DQ[15]
FRC_DQ[13]
URSA_A[10]
FRC_DQ[9]
FRC_DQ[22]
FRC_DQ[28]
FRC_DQ[24]
FRC_DQ[23]
URSA_A[7]
FRC_DQ[31]
FRC_DQ[26]
URSA_A[4]
FRC_DQ[11]
FRC_DQ[6]
FRC_DQ[18]
FRC_DQ[12]
URSA_A[2]
FRC_DQ[21]
FRC_DQ[17]
FRC_DQ[8]
FRC_DQ[7]
FRC_DQ[2]
FRC_DQ[19]
FRC_DQ[4]
URSA_A[5]
URSA_A[3]
EEPROM
HIGH
LOW
[LCM LED Block]
PWM1
ISP Port for MEMC
LOW
HIGH
PI Result
HIGH
PI Result
XTAL
HIGH
GPIO12 GPIO14
Non M+S LVDS LOW LOW
M+S 42" Mini LVDS LOW HIGH
M+S 47" Mini LVDS HIGH LOW
M+S 37" Mini LVDS HIGH HIGH
GPIO8
M+S Option
HIGH
HIGH
I2C
HIGH
SPI
PWM0
SPI FLASH
URSA2/FRC IC
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
56
R316
A_URSA_MCLKE
V9
10uF
C302
0.
1u
F
C316
URSA_BA1
11:R16;V10
B_URSA_BA0
T10
0.
1u
F
C944
URSA_A[0-12]
11
:T
13
URSA_DQS3
11:K23
URSA_DQS2
11:K24
URSA_DQS1
11:Y16
+1.8V_FRC_DDR
0.
1u
F
C311
B_URSA_MCLKE
T10
0.
1u
F
C327
0.
1u
F
C309
0.
1u
F
C952
22
AR306
0.
1u
F
C326
0.
1u
F
C336
A_URSA_CASZ
X16
56
AR317
0.
1u
F
C328
URSA_DQM1
11:W16
0.
1u
F
C337
0.
1u
F
C339
B_URSA_WEZ
Q13
+1.8V_MEMC
0.
1u
F
C340
56
R314
+1.8V_FRC_DDR
+1.8V_FRC_DDR
URSA_DQSB2
11:K24
URSA_DQM3
11:K24
B_URSA_RASZ
R16
A_URSA_BA1
V9
1000pF
C331
0.
1u
F
C307
B_URSA_BA1
T10
10uF
C323
1/16W
33
5%
R309
0.
1u
F
C325
22
AR311
URSA_MCLK1
11:AA15
A_URSA_RASZ
Y13
FRC_DQ[0-31]
11:AB16;E20
22
AR304
URSA_DQSB0
11:X16
0.
1u
F
C324
0.
1u
F
C320
0.
1u
F
C945
URSA_DQS0
11:X16
BLM18PG121SN1D
L300
+1.8V_FRC_DDR
22
AR307
150
OPT
R323
0.
1u
F
C333
1/16W
33
5%
R308
URSA_CASZ
11:P16;S16
+1.8V_MEMC
FRC_DQ[0-31]
11:AB16;AL20
0.
1u
F
C308
0.
1u
F
C946
URSA_ODT
11:K19;Q14
URSA_MCLKE
11:T16;T9
0.
1u
F
C943
56
R312
0.
1u
F
C942
0.
1u
F
C335
22
AR310
A_URSA_BA0
V9
B_URSA_BA0
O15
1/16W
33
5%
R307
+1.8V_FRC_DDR
+1.8V_FRC_DDR
1K1
%
R311
0.
1u
F
C334
22
AR305
URSA_MCLK
11:K20
A_URSA_BA1
AA15
URSA_CASZ
11:P16;W16
URSA_BA0
11:R16;T9
1K1
%
R321
0.
1u
F
C321
0.
1u
F
C341
22
AR313
B_URSA_RASZ
Q13
56
R303
1/16W
33
5%
R319
0.
1u
F
C330
B_URSA_CASZ
R16
56
R302
URSA_DQM2
11:K24
56
R313
150
OPT
R300
1000pF
C306
URSA_RASZ
11:P16;S16
56
AR302
0.
1u
F
C332
10uF
C312
0.
1u
F
C338
0.
1u
F
C948
0.
1u
F
C314
A_URSA_BA0
AA15
+1.8V_FRC_DDR
URSA_DQSB3
11:K23
URSA_MCLKE
11:T16;V10
URSA_ODT
11:K19;Y14
56
R317
B_URSA_BA1
O15
0.
1u
F
C303
1K1
%
R322
10uF
10
V
C301
1/16W
33
5%
R320
56
R306
56
AR301
56
AR315
56
R315
URSA_BA1
11:R16;T9
56
AR316
0.
1u
F
C300
URSA_WEZ
11:R16;V10
1/16W
33
5%
R318
URSA_WEZ
11:R16;T9
0.
1u
F
C304
A_URSA_WEZ
V9
0.
1u
F
C317
56
R305
10uF
10
V
C322
0.
1u
F
C310
B_URSA_CASZ
Q13
+1.8V_FRC_DDR
0.
1u
F
C949
URSA_MCLKZ
11:K20
A_URSA_RASZ
X16
0.
1u
F
C951
22
AR309
URSA_MCLKZ1
11:AB15
56
AR303
0.
1u
F
C947
22
AR312
B_URSA_MCLKE
Q14
+1.8V_FRC_DDR
22
AR308
0.
1u
F
C315
URSA_DQM0
11:W16
10uF
C329
URSA_RASZ
11:P16;W16
A_URSA_CASZ
Y13
1K
1 %
R310
56
AR314
0.
1u
F
C319
A_URSA_MCLKE
Z14
A_URSA_WEZ
Y13
URSA_BA0
11:R16;V10
B_URSA_WEZ
T10
0.
1u
F
C318
0.
1u
F
C950
0.
1u
F
C305
0.
1u
F
C313
56
R304
+1.8V_FRC_DDR
56
R301
56
AR300
URSA_DQSB1
11:Y16
HYB18TC512160CF-1.9
IC300
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
HYB18TC512160CF-1.9
IC301
J2
VREF
J8
CK
H2
VSSQ2
B7
UDQS
N8
A4
P8
A8
L1
NC4
L2
BA0
R8
NC3
K7
RAS
F8
VSSQ3
F3
LDM
P3
A9
M3
A1
N3
A5
K8
CK
R3
NC5
L3
BA1
J7
VSSDL
L7
CAS
F2
VSSQ4
B3
UDM
M2
A10/AP
K2
CKE
R7
NC6
M7
A2
N7
A6
M8
A0
J1
VDDL
K3
WE
E8
LDQS
P7
A11
K9
ODT
A2
NC1
N2
A3
P2
A7
H8
VSSQ1
F7
LDQS
A8
UDQS
R2
A12
L8
CS
E2
NC2
E7
VSSQ5
D8
VSSQ6
D2
VSSQ7
A7
VSSQ8
B8
VSSQ9
B2
VSSQ10
P9
VSS1
N1
VSS2
J3
VSS3
E3
VSS4
A3
VSS5
G9
VDDQ1
G7
VDDQ2
G3
VDDQ3
G1
VDDQ4
E9
VDDQ5
C9
VDDQ6
C7
VDDQ7
C3
VDDQ8
C1
VDDQ9
A9
VDDQ10
R1
VDD1
M9
VDD2
J9
VDD3
E1
VDD4
A1
VDD5
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
DDRB_A[6]
DDR_DQ[12]
DDR_DQ[30]
DDR_DQ[26]
URSA_A[7]
FRC_DQ[26]
DDRB_A[10]
URSA_A[3]
DDRA_A[11]
DDRB_A[0]
DDRA_A[2]
URSA_A[12]
DDR_DQ[25]
DDR_DQ[4]
FRC_DQ[11]
DDRA_A[9]
DDRA_A[0]
URSA_A[0]
DDR_DQ[24]
URSA_A[10]
URSA_A[2]
DDRA_A[8]
DDR_DQ[25]
FRC_DQ[23]
DDRB_A[8]
DDRA_A[8]
DDR_DQ[13]
FRC_DQ[16]
DDR_DQ[18]
DDRB_A[9]
DDRA_A[9]
URSA_A[3]
DDRA_A[2]
FRC_DQ[3]
DDR_DQ[10]
FRC_DQ[12]
URSA_A[5]
URSA_A[2]
DDRB_A[2]
DDR_DQ[20]
DDRA_A[1]
FRC_DQ[15]
DDR_DQ[2]
URSA_A[1]
URSA_A[8]
URSA_A[9]
DDR_DQ[27]
DDR_DQ[21]
FRC_DQ[21]
DDR_DQ[23]
FRC_DQ[1]
DDRA_A[1]
DDRA_A[5]
DDR_DQ[26]
DDRB_A[4]
FRC_DQ[14]
FRC_DQ[13]
DDR_DQ[0-15]
DDRA_A[0-12]
DDR_DQ[28]
DDRA_A[3]
URSA_A[8]
DDR_DQ[22]
DDRA_A[5]
FRC_DQ[0]
DDRB_A[2]
DDRB_A[7]
DDR_DQ[8]
DDRA_A[3]
DDRB_A[9]
DDRB_A[11]
DDRB_A[8]
DDR_DQ[29]
FRC_DQ[9]
DDR_DQ[16]
DDR_DQ[6]
DDR_DQ[1]
DDRA_A[6]
DDR_DQ[6]
FRC_DQ[20]
FRC_DQ[29]
DDRB_A[3]
DDR_DQ[16]
URSA_A[0]
DDRB_A[7]
URSA_A[11]
FRC_DQ[17]
URSA_A[1]
URSA_A[6]
FRC_DQ[24]
DDR_DQ[3]
FRC_DQ[25]
DDRB_A[10]
DDR_DQ[31]
DDRB_A[12]
FRC_DQ[8]
DDR_DQ[30]
DDR_DQ[4]
DDR_DQ[31]
DDRA_A[4]
DDRB_A[12]
DDRA_A[4]
DDR_DQ[5]
FRC_DQ[27]
DDR_DQ[19]
DDRB_A[3]
DDRB_A[5]
FRC_DQ[2]
DDRB_A[0]
DDR_DQ[23]
DDRA_A[12]
DDRB_A[1]
DDR_DQ[29]
DDRA_A[12]
DDR_DQ[1]
FRC_DQ[22]
DDR_DQ[7]
DDR_DQ[20]
DDRB_A[6]
DDRA_A[11]
DDR_DQ[11]
DDR_DQ[0]
DDR_DQ[18]
DDR_DQ[19]
DDR_DQ[10]
FRC_DQ[4]
DDR_DQ[15]
DDRA_A[10]
FRC_DQ[6]
URSA_A[10]
DDR_DQ[15]
DDR_DQ[14]
URSA_A[11]
DDR_DQ[12]
DDRA_A[6]
DDR_DQ[5]
DDRB_A[4]
DDR_DQ[9]
URSA_A[6]
FRC_DQ[7]
FRC_DQ[19]
DDRA_A[10]
URSA_A[4]
DDR_DQ[16-31]
DDR_DQ[17]
DDR_DQ[27]
DDR_DQ[22]
URSA_A[4]
DDR_DQ[13]
DDRB_A[11]
FRC_DQ[31]
DDR_DQ[7]
FRC_DQ[10]
URSA_A[5]
DDRA_A[7]
DDR_DQ[21]
DDR_DQ[14]
FRC_DQ[5]
DDR_DQ[3]
DDRB_A[5]
DDRA_A[7]
DDR_DQ[0]
DDR_DQ[24]
URSA_A[9]
FRC_DQ[18]
DDRA_A[0]
DDR_DQ[11]
DDR_DQ[28]
DDR_DQ[9]
FRC_DQ[30]
DDRB_A[1]
URSA_A[12]
DDR_DQ[8]
FRC_DQ[28]
DDR_DQ[2]
URSA_A[7]
DDRB_A[0-12]
DDR_DQ[17]
resonance Compensation
PI Result
DDR2 1.8V By CAP - Place these Caps near Memory
URSA2 DDR2 IC
Click on the first or last page to see other 42LH40 (CHASSIS:LA92G) service manuals if exist.