JBL JSR 400 Service Manual ▷ View online
3 5
Dolby Pro-Logic
Ò
A/V Receiver
JSR-400
WIRING DIAGRAM
JSR-400
WIRING
DIAGRAM
5
5
4
4
3
3
2
2
1
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
VIDEO
PCB
ASS
’Y
01
12-000-1613
TUNER
PCB
ASS
’Y
01
12-000-181-2
11
12-000-01
1
VOLUME
PCB
ASS
’Y
0122-002-1612
TONE
PCB
ASS
’Y
01
12-002-1614
CONTROL
PCB
ASS
’Y
01
12-000-191
11
12-000-013
MAIN
PCB
ASS
’Y
01
12-002-151-2
11
12-000-017
HEAD
PHONE
PCB
ASS
’Y
01
12-000-1615
POWER
TRANSFORMER
POWER
SUPPL
Y
PCB
ASS
’Y
01
12-000-161
1
AC
INPUT
WA
4
WA
3
CN1
1
WA
1
WA
2 WA
5
BLU
BLU
GRY
GRY
YEL BLK YEL
CN5
CN10
CN101
CN102
CN7
CN6
CN4
CN3
WA
8
WA
7
WA
4
WA
11
WA
3
CN9
W
A12
CN2
WA
4
WA
1
WA
10
WA
2
WA
8
RED GRN RED
3 6
Dolby Pro-Logic
Ò
A/V Receiver
JSR-400
INTEGRATED CIRCUIT DIAGRAMS 1
Main PCB - IC5
Video
(LC4966)
QUAD BILATERAL SWITCH
PCB - IC5 (LC4966)
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
5
2
6
3
7
4
14
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
10
13
9
12
8
11
VDD CONTA CONTD
VSG
CONTB
OUT/IN
OUT/IN
OUT/IN
OUT/IN
CONTC
IN/OUT
IN/OUT
IN/OUT
IN/OUT
SW A
SW D
SW B
SW C
{
{
{
{
SW
A
SW
D
SW
B
SW
C
Input
Auto-
balance
Control
X1
X1
Center/
Operating
Mode
Control
Adaptive
Matrix
Lp
Rp
Cp
Lt
Lt
Rt
V
LR
V
CS
7kHz
LPF
Modified
Dolby
B.N.R.
Noise
Sequencer
L Input
R Input
L+R
L-R
L+R
L-R
Delay
SW2
S'
SIPO
Noise seq.
By-pass Line
Left
Right
Center
Right
Center
Surround
Idsw
REQ
SCX
DATA
Digital GND
V
REQ
SCX
DATA
Digital GND
V
DD
CT
ST
Trimmer
Trimmer
Sp
Pd
NEG/POS
2/3/4ch
CenterON/OFF
Nor/Pha/Wi
OUTPUTS
Main PCB IC10 - (NJW1102)
D/S DECODER
Control PCB IC1 - (CXP82712)
+5V
NC
REMOCON
POWER OFF
OPTION 2
OPTION 1
OPTION 0
-27V
GRID 01
GRID 02
GRID 03
GRID 04
GRID 05
GRID 06
GRID 07
GRID 08
SEG 16
SEG 15
SEG 14
SEG 13
SEG 12
SEG 11
SEG 10
SEG 09
SEG 08 / KS01102
SEG 07 / KS1
SEG 06 / KS2
SEG 05 / KS3
SEG 04 / KS4
SEG 03 / KS5
SEG 02 / KS6
SEG 01
STEREO
TUNED
+5V
NC
P/F DI
P/F CL
PLL CE
A-MUTE
POWER ON
SP FRONT
VOL.UP
VOL. DN
PO.IND
R/C MUTE
VIDEO
VCR
KR 00
KR 01
KR 02
KR 03
DOLBY
BY-PASS
1102 DATA
1102 SCK
REQ
7821 CE
T-MUTE
OPTION
RESET
X-TAL
X-TAL
GND
3 7
Dolby Pro-Logic
Ò
A/V Receiver
JSR-400
INTEGRATED CIRCUIT DIAGRAMS 2
2
1
11
6
11
14
15
12
13
12
XIN
XOUT
FMIN
AMIN
PD1
PD2
VDD1
VDD2
VSS
SYC
3
4
5
7
8
9
CE CL DATA
BO1
BO2
BO3
6
Shift Register - Latch
Programable Divider
Reference Divider
Phase Detector
Charge Pump
Tuner PCB IC2 - (LM7001)
(PLL Synthesizer and Controller)
Terminal Description
Pin No.
Terminal
Description
1
XOUT
Connect to the 7.2 Mhz crystal oscillator.
2
XIN
3
CE
Chip enable terminal. Connect to the PLL terminal of microprocessor.
4
5CL
Serial clock input terminal. Connect to the CLOCK terminal of microprocessor.
5
DATA
Serial data input. Connect to the DATA terminal of micro processor.
6
SYN
Not used
7
AUTO/MONO
AUTO/MONO selection output terminal. “L” when FM.
8
FM
FM band control output terminal. “L” when FM.
9
AM
AM band control output terminal. “L” when AM.
10
AMIN
AM local oscillator input terminal.
11
FMIN
FM local oscillator terminal.
12
V
DD
1
Power supply terminal for back-up.
13
V
DD
2
Power supply terminal.
14
PD1
Charge pump output of the phase detector which constitues the PLL. High level is output when the divided
local oscillator frequency is higher than the reference frequency. In the opposite case, low level is output.
Floating occurs when the frequency matched. The output is applied to the variable capacitor diode in the
local oscillator through the low pass filters.
15
PD2
16
V
SS
Ground terminal.
3 8
Dolby Pro-Logic
Ò
A/V Receiver
JSR-400
INTEGRATED CIRCUIT DIAGRAMS 3
DEM
MOD
16K
SRAM
AUTO
RESET
OSCILLATOR
MAIN CONTROL
DELC
CLOCK
RESET
D1
DO0
DO1
M0
M1
OP1
4.7k
COMP
LPF1
1/2 V
CC
-
-
-
+
+
+
-
-
+
+
4.7k
OP2
LPF2
LPF1IN LPF1OUT OP1OUT OP1IN
OC1
OC2 OP2IN OP2OUT LPF2IN LPF2OUT
XIN
XOUT
REQ SCK DATA IDSW
REF
IDFLAG
TEST1 TEST2
DGND AGND
NJU9702
1
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
23
22
21
20
19
18
17
16
15
14
13
DIGITAL V
DD
OSCILLATOR INPUT
OSCILLATOR OUTPUT
REQ
SCK
DATA
IDSW
IDFLAG
TEST1
TEST2
TEST2
DIGITAL GND
ANALOG GND
ANALOG V
CC
LPF1IN
LPF1OUT
OP1OUT
OP1IN
REF
CC1
CC2
OP2IN
OP2OUT
LPF2IN
LPF2OUT
LPF1OUT
OP1OUT
OP1IN
REF
CC1
CC2
OP2IN
OP2OUT
LPF2IN
LPF2OUT
VDD V
CC
DELAY TIME
CONTROL
22
23
21
20
18
17
16
15
14
13
19
2
3
4
5
6
7
8
9
10
11 12
1
24
Main PCB IC11 - (NJU9702) D/S DELAY
Terminal Description
Pin No.
Symbol
Functions
1
V
DD
Voltage Supply for Digital Block V
DD
=5(V)
11
DGND
Digital GND DGND=0(V)
24
V
CC
Voltage supply for Analog Block V
CC
=5(V)
12
AGND
Analog GND AGND=0(V)
19
REF
Analog Reference Voltage REF=1/2
×
V
CC
2
X
IN
Oscillator Input Terminal
3
X
OUT
Oscillator Output Terminal
Connects to 2MHz ceramic Oscillator
4
REQ
Data Request Input Terminal
5
SCK
Serial Data Shift Clock Input Terminal
6
DATA
Serial Data Input Terminal.
7
IDSW
ID Switch (ID Code When Connect to the Common Bus)
8
IDFLAG
ID Flag (Data Input Confirmation and Serial Data Output)
18
CC1
Current Control 1 Modulator
ADM Controller
17
CC2
Current Control 2 Demodulator
9, 10
TEST1, 2
Test Terminal (Normally Connects to the GND)
23
LP1IN
Lowpass Filter 1 Input
Input Side
Constitue a Lowpass
Filter with external C
and R.
22
LPF1OUT
Lowpass Filter 1 Output
14
LPF2IN
Lowpass Filter 2 Input
Output Side
13
LPF2OUT
Lowpass Filter 2 Output
20
OP1IN
OP-AMP 1 Input
Input Side
Constitute an Integrator
with external C.
21
OP1OUT
OP-AMP 1 Output
16
OP2IN
OP-AMP 2 Input
Output Side
15
OP2OUT
OP-AMP 2 Output
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