Harman Kardon HD 970 (serv.man9) Service Manual ▷ View online
REV. 0
AD1955
PIN FUNCTION DESCRIPTIONS
Pin No.
I/O
Mnemonic
Description
1
DVDD
Digital Power Supply Connected to Digital 5 V Supply
2
Input
LRCLK/EF_WCLK
Left/Right Clock Input for Input Data in PCM Mode
Word Clock in External Filter Mode
Word Clock in External Filter Mode
3
Input
BCLK/EF_BCLK
Bit Clock Input for Input Data in PCM Mode
Bit Clock Input in External Filter Mode
Bit Clock Input in External Filter Mode
4
Input
SDATA/EF_LDATA
MSB First, Twos Complement Serial Audio Data
Two Channel (left and right), 16-Bit to 24-Bit Data in PCM Mode
Left Channel Data in External Filter Mode
Two Channel (left and right), 16-Bit to 24-Bit Data in PCM Mode
Left Channel Data in External Filter Mode
5
Input
EF_RDATA
Not used in PCM Mode
Right channel data in External Filter Mode
Right channel data in External Filter Mode
6
I/O
DSD_SCLK
Serial Clock Input for DSD Data. This clock should be 64
44.1 kHz,
2.8224 MHz or 128
44.1 kHz, 5.6448 MHz in Normal Mode, 128
44.1 kHz, 5.6448 MHz or 256
44.1 kHz, 11.2896 MHz in Phase Mode.
7
Input
DSD_LDATA
DSD Left Channel Data Input
8
Input
DSD_RDATA
DSD Right Channel Data Input
9
I/O
DSD_PHASE
DSD Phase Reference Signal. This clock should be 64
44.1 kHz,
2.8224 MHz. If not used, this pin should be connected low.
10
AGND
Analog Ground
11
Output
IOUTR+
Right Channel Positive Analog Output
12
Output
IOUTR–
Right Channel Negative Analog Output
13
Output
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10
voltage reference with parallel 10
µF and 0.1 µF capacitors to AGND.
14
IREF
Connection Point for External Bias Resistor
15
AVDD
Analog Power Supply Connected to Analog 5 V Supply
16
Output
FILTB
Filter Capacitor Connection with Parallel 10
µF and 0.1 µF Capacitors to AGND
17
Output
IOUTL–
Left Channel Negative Analog Output
18
Output
IOUTL+
Left Channel Positive Analog Output
19
AGND
Analog Ground
20
Output
ZEROR
Right Channel Zero Flag Output. This pin goes high when the right channel
has no signal input or the DSD mute pattern is detected.
has no signal input or the DSD mute pattern is detected.
21
Output
ZEROL
Left Channel Zero Flag Output. This pin goes high when the left channel has
no signal input or the DSD mute pattern is detected.
no signal input or the DSD mute pattern is detected.
22
Input
MUTE
Mute. Assert high to mute both stereo analog outputs. Deassert low for nor-
mal operation.
mal operation.
23
Input
PD/RST
Power Down/Reset. The AD1955 is placed in a reset state and the digital
circuitry is powered down when this pin is held low. The AD1955 is reset on
the rising edge of this signal. The serial control port registers are reset to the
default values. Connect high for normal operation.
circuitry is powered down when this pin is held low. The AD1955 is reset on
the rising edge of this signal. The serial control port registers are reset to the
default values. Connect high for normal operation.
24
Input
CDATA
Serial Control Input, MSB First, Containing 16 Bits of Unsigned Data. Used
for specifying control information and channel-specific attenuation.
for specifying control information and channel-specific attenuation.
25
Input
CLATCH
Latch Input for Control Data
26
Input
CCLK
Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
edge of CCLK. CCLK may be continuous or gated.
27
Input
MCLK
Master Clock Input. Connect to an external clock source.
28
DGND
Digital Ground
U19 ADSP21532 DSP
ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. A
|
|
January 2005
Table 39. 176-Lead LQFP Pin Assignment (Numerically by Lead Number)
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
1
GND
41
GND
81
TX
121
ADDR19
161
AMS0
2
GND
42
GND
82
RX
122
ADDR18
162
ARDY
3
GND
43
GND
83
EMU
123
ADDR17
163
BR
4
VROUT2
44
GND
84
TRST
124
ADDR16
164
SA10
5
VROUT1
45
VDDEXT
85
TMS
125
ADDR15
165
SWE
6
VDDEXT
46
PF5
86
TDI
126
ADDR14
166
SCAS
7
GND
47
PF4
87
TDO
127
ADDR13
167
SRAS
8
GND
48
PF3
88
GND
128
GND
168
VDDINT
9
GND
49
PF2
89
GND
129
GND
169
CLKOUT
10
CLKIN
50
PF1
90
GND
130
GND
170
GND
11
XTAL
51
PF0
91
GND
131
GND
171
VDDEXT
12
VDDEXT
52
VDDINT
92
GND
132
GND
172
SMS
13
RESET
53
SCK
93
VDDEXT
133
GND
173
SCKE
14
NMI
54
MISO
94
TCK
134
VDDEXT
174
GND
15
GND
55
MOSI
95
BMODE1
135
ADDR12
175
GND
16
RTXO
56
GND
96
BMODE0
136
ADDR11
176
GND
17
RTXI
57
VDDEXT
97
GND
137
ADDR10
18
VDDRTC
58
DT1SEC
98
DATA15
138
ADDR9
19
GND
59
DT1PRI
99
DATA14
139
ADDR8
20
VDDEXT
60
TFS1
100
DATA13
140
ADDR7
21
PPI_CLK
61
TSCLK1
101
DATA12
141
ADDR6
22
PPI0
62
DR1SEC
102
DATA11
142
ADDR5
23
PPI1
63
DR1PRI
103
DATA10
143
VDDINT
24
PPI2
64
RFS1
104
DATA9
144
GND
25
VDDINT
65
RSCLK1
105
DATA8
145
VDDEXT
26
PPI3
66
VDDINT
106
GND
146
ADDR4
27
PF15
67
DT0SEC
107
VDDEXT
147
ADDR3
28
PF14
68
DT0PRI
108
DATA7
148
ADDR2
29
PF13
69
TFS0
109
DATA6
149
ADDR1
30
GND
70
GND
110
DATA5
150
ABE1
31
VDDEXT
71
VDDEXT
111
VDDINT
151
ABE0
32
PF12
72
TSCLK0
112
DATA4
152
AWE
33
PF11
73
DR0SEC
113
DATA3
153
ARE
34
PF10
74
DR0PRI
114
DATA2
154
AOE
35
PF9
75
RFS0
115
DATA1
155
GND
36
PF8
76
RSCLK0
116
DATA0
156
VDDEXT
37
PF7
77
TMR2
117
GND
157
VDDINT
38
PF6
78
TMR1
118
VDDEXT
158
AMS3
39
GND
79
TMR0
119
BG
159
AMS2
40
GND
80
VDDINT
120
BGH
160
AMS1
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