Harman Kardon DVD 21 (serv.man10) Service Manual ▷ View online
+12V
+5V
+5V
VIDEOFORMAT
TVFORMAT0
TVFORMAT1
FRONT_L2
FRONT_R2
2C6
20PF
2FB3
2C3
0.1UF
2FB6
2R8
2R7
3.3K 5%
2R9
1K
2C9
20PF
C
B
E
4.7K
3
2
1
2Q3
DTC343TK
SMT 3
DTC343TK
ROHM
ROHM
S
C
A
R
T
CO
NN
E
C
T
O
R
B
A
C
K
PAN
E
L
VI
EW
2J2
SCART CONNECTOR, RIGHT ANGLE, FEMALE
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
2
AOR
AOL
AGND
BGND
AIL
B
SWT CH
GGND
CLKOUT
G
DATA
RGND
DATAGND
R
BLNK
VGND
BLNKGND
VOUT
VIN
SHIELD
AIR
2R3
1K
C
B
E
4.7K
3
2
1
2Q2
DT C343TK
SMT3
DT C343TK
ROHM
ROHM
2R15
4.7K
2J3
IR IN/OUT
6
3
2
4
5
1
2C12
47uF/16V
2D1
1N4148
1
2
2R13
390R
2R11
10K
2R10
10K
2U1
1
3
2
4
P1
P3
P2
P4
2FB8
2C11
680PF
2C1
0.1UF
C
B
E
4.7K
3
2
1
2Q1
DTC343T K
SMT3
DTC343T K
ROHM
ROHM
2FB7
2C7
20PF
2FB4
2C10
680PF
2R6
1K
2C8
20PF
2FB5
2C2
0.1UF
2FB1
2FB2
2C5
20PF
2C4
20PF
2R1
3.3K 5%
2R4
3.3K 5%
CON 22 PIN TH 1MM
2J1
1
2
3
4
9
8
7
6
5
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
FRONT_R2
GND
FRONT _L2
GND
Cb/B
GND
GND
GND
Cr/R
GND
Y/G
GND
CVBS
GND
RXD1
CTS0-
TVFORMAT1
TVFORMAT0
VIDEOFORMAT
5V
12V
2R2
3.3K
2R5
3.3K
C
B
E
3
1
2
2Q4
BC858
2R14
270R
2R12
4.7K
SCART
VIDEOFORMAT
~6V
TVFORMAT1
1
~0V
TVFORMAT0
~0V
1
0
SCART Inactive (Standby)
1
0
1
0
0
~12V
SCART Active Auto Switch to 4:3 Aspect Ratio
TV FUNCTION
CONTROL
VOLTAGE
VOLTAGE
SCART Active Auto Switch to 16:9 Aspect Ratio
TV FUNC TI ON
DISPLAY RGB (CVBS V IDEO is BLANKED)
LOW (0V)
HIGH (5V)
DIS PLAY CVBS (IF ACT IV E)
EA UX40
VS( EA UX31)
HS( EA UX30)
XM5
MOUNTINGHOLE
1
.
XM8
MOUNTINGHOLE
1
.
XM7
MOUNTINGHOLE
1
.
XM6
MOUNTINGHOLE
1
.
NON-PLATED 125mil DIA. 250mil RING with 8 vias
XIO ALLOCATION TABLE
MOUNTING / TOOLING HOLES
SIGNAL
NAME
PIN
NAME
X-BUS
CONN
PIN
CONN
PIN
NOTES
I/O
APPLICATION
First release. Preliminary form.
2002-JUN-19
Assembly
Revision
Revision History
SCH. REV: 1.10
Description of Changes
Date
3.4V
1.8V
Core DIG. PWR.
2.5V
Pantera-2 Plus
2.5V
108
5V
0.8V
VAA
102
Function
*
NDV8501
1.6V
1.8V
3.3V
VDD
DAC Analog
Chip
5V
Pin name
3.3V
NDV8601
Regulator
power
dissipation
power
dissipation
107
117
For correct regulation, LM1117 requires a minimum 1.2V voltage drop between the
input and output.
Output
current
OSCVDD
NDV860X
DAC Supply
Regulator
drop
MVCKVDD
3.3V
NDV8501
3.3V
0.8W
Regulator
input
VDDIO
2.5V
PANTERA POWER SUPPLIES
1.2W
Diode
drops
in PS
drops
in PS
I/O DIG. PWR.
1.8V
0.5A
3.3V
3.3V
Pin #
0.7A
1 10 19 27 36 44 53 62 75 91 125
140 154 169 181 196 210 224
233
140 154 169 181 196 210 224
233
101
2.5V
Pantera-2
1.6V
4 34 77 89 135 159 192 212
8 pins
Oscillator
VAA3
1.7V
3.3V
Main & Video PLLs
Audio PLL
VDDDAC
3.3V
19 pins
4.2V
ACLKVDD
1.8V
* DAC Analog supply for Pantera-2. DAC Digital supply for the others.
113
DAC Digital
Source
in PS
unit
in PS
unit
93
OUT
Chip select for the Front Panel Microcontroller. Active LOW.
XIO5
88
XIO9
IN
96
IN/OUT
XIO7
In a custom application, do not use these pins
as a chip select since the FPGA development
does not support it.
as a chip select since the FPGA development
does not support it.
OUT
XIO1
XIO2
REQ
N/A
XIO10
XIO3
FLDCS-
XIO8
AUDIOMUTE
EECS
Audio MUTE signal. Active HIGH. When HIGH, all
audio outputs are muted simultaneously.
XIO4
ENABLE
Wakeup and Key matrix interrupt input, 5V/3.3V CMOS level. Input
from the Front Panel "Wakeup/Interrupt Circuit". When no key is
pressed, XIO8 is high. When any key or combinations of keys are
pressed, XIO8 will be low. After the key(s) are released, the signal
will return to high after about 1ms.
from the Front Panel "Wakeup/Interrupt Circuit". When no key is
pressed, XIO8 is high. When any key or combinations of keys are
pressed, XIO8 will be low. After the key(s) are released, the signal
will return to high after about 1ms.
OUT
N/A
In a custom application, do not use this pin as a chip
select since the FPGA development does not support it.
PCS0-
WKUP-
85
89
97
N/A
Front End Drive Reset. SW programmable. The signal polarity
depends on the drive used.
Control Intel Flash Vpp
IN
100
OUT
81
XIO14
OUT
XIO6
Chip select for the 192KHz audio DAC only. Active LOW.
XIO12
FERST-
Output from Pantera. This is TX_REQ- going to the FE.
XIO11
OUT
NC
OUT
Input to Pantera. This is TX_ENABLE- from the FE.
OUT
Chip select for the EEPROM. Active HIGH.
Do not use this pin.
XIO13
192KDACCS-
Dedicated signal for SLAVE mode development. This pin must
NOT be used in the application.
OUT
SLVINT-
92
OUT
FLASHCS0-
84
Chip select fo FLASH memory, first bank
77
OUT
RTS0
OUT
96
ARESET-
AUDIO RESET for all DACs
95
CT
S
0
IN
OP_FORMAT
Selects the Output Format of the Video depending on build (INT gen.)
TVFORMAT0
TVFORMAT1
Control SCART Pin8 Switch Level
Control SCART Pin8 Switch Level
FLASHPROG
VIDEOFORMAT Control SCART Pin16,To Select the Video Output Format is
RGB or CVBS
OUT
V3.3
ACK-
P2
SRST-
P2,5,10
PCS0-
P2
LHLDA
P2
PWE3-
P2
ALE
P2,5
SCLKR
P2
FLASHCS0-
P5
XIO[11:1]
P2,3,7,9
PWE1-
P2
LA[3:0]
P2,5
AD[31:0]
P2,5
RD-
P2,5
PWE2-
P2
PWE0-
P2,5
LHLD
P2
RSTP-
P2
XIO6
AD12
SRAMCS-
PCS0-
PCS0-
AD4
LA1
RD-
AD26
AD5
XIO3
LA0
AD17
AD22
XIO10
LA1
SRST-
PCS0-
PWE2-
LHLDA
XIO8
AD0
AD10
AD21
AD19
AD28
AD11
AD6
AD24
AD3
AD8
AD14
LA3
LHLD
XIO7
AD7
AD13
AD30
AD15
XIO5
AD[31:0]
AD29
AD25
AD20
AD9
AD4
PWE3-
LHLDA
LA0
AD2
SCLKR
XIO11
AD18
LA2
PWE1-
XIO1
FLASHCS0-
XIO4
AD31
LHLD
AD23
FLASHCS0-
LA2
AD27
ACK-
ALE
PWE3-
PWE2-
PWE1-
PWE0-
PWE2-
PWE1-
PWE0-
SCLKR
ALE
ACK-
RD-
LA3
AD1
AD16
PCS0-
PWE0-
XIO9
XIO[11:1]
LA0
LA2
LA3
LA1
LA[3:0]
RSTP-FPGA-
RSTP-
C89
10UF/10V
R15
3.3K N/A
R12
3.3K
R54
0R N/A
0R N/A
R14
3.3K N/A
XJP1
P/N: 179030-4
100 PIN, 0.8MM PIT CH
MANUFACT URER: AMP
AMP179030_4
J7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
+5V
+5V
+5V
+5V
+3.3V
+3.3V
+3.3V
+3.3V
SRST-
SPARE1
RSTP-
SPARE2
GND
GND
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
GND
AD23
PWE3-
AD22
GND
AD21
AD20
AD19
AD18
AD17
GND
AD16
PWE2-
AD15
GND
AD14
SCLK
AD13
GND
AD12
ACK-
AD11
GND
AD10
AD9
AD8
GND
AD7
PWE1-
AD6
GND
AD5
AD4
AD3
AD2
AD1
AD0
GND
GND
PWE0-
ALE
GND
GND
LA0
LA1
LA2
LA3
GND
GND
RD-
LHLDA
GND
GND
LHLD
PCS0-
GND
GND
SRAMCS-
XIO1
GND
GND
XIO3
XIO4
GND
GND
XIO5
XIO6
GND
GND
XIO7
XIO8
GND
GND
XIO9
XIO10
GND
GND
XIO11
1
2
3
4
JP1
R52
470R
TP15
RST
VCC
GND
VCC
GND
S3 B
U12
LM809M3-2.63
3
1
2
R13
3.3K N/A
R57
100K
100K
R38
3.3K N/A
R48
470R
470R
C44
0.1UF
PRODUCTION (FLASH)
1-2
Note: For production version, the
jumper is not assembled. Instead,
assemble the zero-Ohm resistor.
jumper is not assembled. Instead,
assemble the zero-Ohm resistor.
JUMPER SETTING
SW DEVELOPMENT (SRAM)
THESE WIRES MAY BE LONG IF NECESSARY. IF
THE FUNCTION NEEDS TO BE CONFIGURABLE,
A SWITCH MAY BE ADDED BETWEEN THE
RESISTOR AND GROUND. THE SWITCHES MAY
BE LOCATED NEAR THE BACK PANEL.
THE FUNCTION NEEDS TO BE CONFIGURABLE,
A SWITCH MAY BE ADDED BETWEEN THE
RESISTOR AND GROUND. THE SWITCHES MAY
BE LOCATED NEAR THE BACK PANEL.
3-4
SHORT WIRES
POWER-UP CONFIGURATION RESISTOR
USER DEFINED POWER-UP
CONFIGURATION RESISTORS
Used as BOARD-ID
configuration resistors in this
board. The resistors are used
to configure the SW
automatically. This board ID
is 0x8.
configuration resistors in this
board. The resistors are used
to configure the SW
automatically. This board ID
is 0x8.
THIS CONNECTOR (XBUS) IS USED FOR SW DEVELOPMENT, FLASH PROGRAMMING, AND
CONNECTING WITH OTHER HW DEVELOPMENT PLATFORMS AND LOGIC ANALYZER.
Pull down resistor on AD4 allows
selection of 16/32 bit BootPromWidth.
AD[4] has internal pull up resistor.
Default= 32 bit ROM width.
selection of 16/32 bit BootPromWidth.
AD[4] has internal pull up resistor.
Default= 32 bit ROM width.
IMPORTANT NOTE !
THIS CONNECTOR IS MANDATORY ON THE FIRST REVISION OF THE BOARD TO
ALLOW SW DEVELOPMENT. WITHOUT THIS CONNECTOR IT IS IMPOSSIBLE TO
DEVELOP SW FOR THE CUSTOMER SPECIFIC APPLICATIONS. LATER, AFTER
THE DESIGN IS FINALIZED, THE CONNECTOR MAY BE REMOVED.
XBUS Connector
to be Mounted On
Bottom Of PCB
R130
AD[4]
BOOT MODE
32-bits
1
NO
0
16-bits
YES
/X
B
U
S
FL
A
S
H
POWER-ON
RESET &
SUPERVISOR
RESET &
SUPERVISOR
