DOWNLOAD Harman Kardon CDR 20 (serv.man18) Service Manual ↓ Size: 536.99 KB | Pages: 23 in PDF or view online for FREE

Model
CDR 20 (serv.man18)
Pages
23
Size
536.99 KB
Type
PDF
Document
Service Tips
Brand
Device
Audio
File
cdr-20-sm18.pdf
Date
PREV: Harman Kardon CDR 20 (serv.man17) Service Manual / Technical Bulletin

Harman Kardon CDR 20 (serv.man18) Service Tips ▷ View online

LG Electronics DAV Engineering LAB.
OLD FPGA
(ADR-600)
DEC
DEC & ENC
SRC
u-COM
CDP
CDRW
FPGA
u-COM
MUX
MUX
DAC
MUX
ADC
ANALOG
DAC
Coax & Opt(F)
Coax(B)
R
JACK
SW
Opt(B)
R
R
R
SW
R
R
R
R
HDCD
& MP3
MUX
MUX
MUX
NEW
FPGA
MDA_CLK
MDA_DATA
MDA_LRCK
Phone
CDP-IN
CDR-IN
CDP-OUT
CDR-OUT
Jack Name
FRONT
MUX
MUX
MUX
DIGI_3_IN
OPT_FR_IN
DIG_IN
P_BCK/MP_CLK
P_DATA/MP_DATA
P_LRCK/MP_REQ
MUX
DIG_BK_IN
CDP_DOUT
CS_CLK
CS_LRCK
CS_DATA
F_CLK
F_LRCK
F_DATA
F_MPDATA
F_MPCLK
F_MPREQ
DA_RCLK
DA_RLRCK
DA_RDATA
DA_PCLK
DA_PLRCK
DA_PDATA
AD_CLK
AD_LRCK
AD_DATA
OP
T
_
BK
_
IN
F_DOUTR
F_DOUTP
DOUT
Audio Signal Flow Diagram (CDR 30); Physical view point
ATAPI
ATAPI
Selected by Jack
automatically
at Front board
PCB Border
in ADR-600
I/O
FRONT
DIG_FR_IN
HP_L
HP_R
LG Electronics DAV Engineering LAB.
DEC
DEC/
ENCODER
SRC
u-COM
FPGA
u-COM
HDCD
& MP3
Audio Signal Flow Diagram (CDR 30); Logical view point
I/O    BOARD
FRONT    BOARD
MDA_CLK
MDA_DATA
MDA_LRCK
OPT_FR_IN
DIG_IN
DIGI_3_IN
P_BCK/MP_CLK
P_DATA_MP_DATA
P_LRCK/MP_REQ
OPT_BK_IN
CDP_DOUT
CS_CLK
CS_LRCK
CS_DATA
F_CLK
F_LRCK
F_DATA
F_MPDATA
F_MPCLK
F_MPREQ
DA_PCLK
DA_PLRCK
DA_PDATA
DA_RCLK
DA_RLRCK
DA_RDATA
AD_CLK
AD_LRCK
AD_DATA
F_DOUTP
F_DOUTR
DOUT
ATAPI
(MP3)
SRC_TXP
SRC_RXP
SRC_CLK
SRC_LRCK
SRC_DATA
V_LEVEL
ATAPI
(MP3)
OUTPUT
MUXs
HOST I/F
INPUT
ADDR
OUTPUT
ADDR
INPUT
MUXs
HOST I/F
HP_L
HP_R
DIG_BK_IN
(HDCD INFOR)
KEY IN
(INPUT SELECT)
CDR_MUTE
CDR_EMPH
CDP_MUTE
CDP_EMPH
AUD_DA_MUTE
EXTRMC
HOST I/F
NEW
FPGA
¤ Volume Control Block
is excluded in this Diagram
LG Electronics DAV Engineering LAB.
CDRW Brd.
I/O Brd.
CDP Brd.
Connector Diagram (CDR 30)
OPT
_
IN
GND
MC
L
K
DA_
R
C
L
K
DA_
R
L
R
C
K
GND
S_
MC
K
GND
DA_
PC
L
K
DA_
PDAT
A
DA_
R
DAT
A
GND
GND
AD_
C
L
K
AD_
L
R
C
K
AD_
DAT
A
DA_
PL
R
C
K
CD
R
_
M
U
T
E
GND
AUD_
DA_
M
U
T
E
CD
P
_
M
U
T
E
C
D
P_
E
M
PH
GND
HP
_
R
HP
_
L
PW
R
_
M
U
T
E
CD
R
_
E
M
P
H
GND
F_
DOU
T
R
F_
DOU
T
P
GND
DI
G_
B
K
_
IN
1
11
21
31
REC_CLK
REC_TXD
REC_RXD
GND
CDP_33M
GND
P_BCK/MP_CLK
P_DATA/MP_DATA
P_LRCK/MP_REQ
GND
CDP_DOUT
DIG_BK_IN
GND
DIGI_3_IN
PWR_MUTE
GND
EXT_RMC
AUD_DA_MUTE
CDP_MUTE
CDP_EMPH
GND
HP_R
HP_L
1
11
21
PW
R
_
C
T
L
FL
_
S
C
K
F
L
_O
E
F
L
_CE
FL
_
S
DI
RE
M
O
_
S
IG
DGND
KE
Y_
IN
2
KE
Y_
IN
1
KE
Y_
IN
0
1
10
F+
GND
34
-
34
V
GND
F-
+
5
V
GNDF
5
VF
1
8
D
5
V
A
5
V
DGND
GND
12
V
MGND
1
6
PI
C
K
-U
P
SL
ED
S
P
INDL
E
PW
R
_
C
T
L
5
V(
U
-C
O
M)
12
VM
DGND
MGND
5
VM
AGNS
5
VA
PW
R
_
FAI
L
1
9
PI
C
K
-U
P
S
P
INDL
E
F2
O
P
T
_
F
R
_IN
+
5
V
DGND
1
6
DI
G_
IN
DGND
F4
HP
_
R
HP
_
G
N
D
HP
_
L
1
3
F5
F1
F3
F2
6
F3
F3
F3
CDRW
Down
Load
Load
1
24
Sled
DRAGON
PWR Brd.
10
1
1
31
F+
GND
34
-
34
V
F-
GNDF
5
VF
1
F4
RG
N
D
RO
U
T
LO
U
T
L
GND
LI
N
RI
N
1
6
F1
DI
G_
IN
The new Power 
Line(+5V/1A) will be 
included in this 
connection to satisfy the 
CDRW part’s power 
consumption. 
+
5
V
+5V
+5V
Th
e c
on
ne
cti
on
 m
ust
 be
 
de
sig
ne
d t
o m
eet
 EM
I 
gu
ide
-lin
es 
an
d t
o  
im
pr
ov
e t
he
ass
em
bli
ng
 
eff
ici
en
cy.
LG Electronics DAV Engineering LAB.
OLD FPGA
DEC
DEC & ENC
SRC
u-COM
CDP
CDRW
FPGA
u-COM
MUX
MUX
DAC
MUX
ADC
ANALOG
DAC
Coax & Opt(F)
Coax(B)
R
JACK
SW
Opt(B)
R
R
R
SW
R
R
R
R
HDCD
& MP3
MUX
MUX
MUX
NEW
FPGA
HDCD,
CDDA
Phone
CDP-IN
CDR-IN
CDP-OUT
CDR-OUT
Jack Name
FRONT
MUX
MUX
MUX
DIGI_3_IN
MUX
OP
T
_
BK
_
IN
F_DOUTR
F_DOUTP
Signal Flow 1-1 (CDR 30)- Opt Rec(Front & Back); 
Opt=HDCD or CDDA , CDP=Play
I/O
FRONT
ATAPI
ATAPI
OPT_FR_IN
CDP_DOUT
MUX
Front Opt
Only
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