Harman Kardon BDP 10 Service Manual ▷ View online
D DR1_A13
D DR1_A11
D DR1_A10
D DR1_A9
D DR1_A8
D DR1_A7
D DR1_A6
D DR1_A5
D DR1_A4
D DR1_A3
D DR1_A2
D DR1_A1
D DR1_A0
D DR1_A12
D DR1_A13
D DR1_A11
D DR1_A10
D DR1_A9
D DR1_A8
D DR1_A7
D DR1_A6
D DR1_A5
D DR1_A4
D DR1_A3
D DR1_A2
D DR1_A1
D DR1_A0
D DR1_A12
DDR1_CLK1
DDR1_DQM2
DDR1_DQM3
DDR1_DQS2N
DDR1_DQS2P
DDR1_DQS3N
DDR1_DQS3P
DDR1_ODT23
DDR1_WEN
DDR1_CASN
DDR1_RASN
DDR1_CS1N
D DR1_CKE
DDR1_CLK1N
DDR1_CLK1
DD R1_BA0
DD R1_BA1
DD R1_BA2
DD R1_BA2
DD R1_BA1
DD R1_BA0
DDR1_CLK0
DDR1_CLK0N
D DR1_CKE
DDR1_CS0N
DDR1_RASN
DDR1_CASN
DDR1_WEN
DDR1_ODT01
DDR1_DQS1P
DDR1_DQS1N
DDR1_DQS0P
DDR1_DQS0N
DDR1_DQM1
DDR1_DQM0
+VREF_DDR
DDR1_D14
DDR1_D10
DDR1_D13
DDR1_D9
DDR1_D12
DDR1_D11
DDR1_D15
DDR1_D8
DDR1_D6
DDR1_D5
DDR1_D1
DDR1_D0
DDR1_D7
DDR1_D4
DDR1_D2
DDR1_D3
DDR1_D26
DDR1_D28
DDR1_D29
DDR1_D30
DDR1_D24
DDR1_D31
DDR1_D27
DDR1_D25
DDR1_D22
DDR1_D17
DDR1_D20
DDR1_D18
DDR1_D19
DDR1_D16
DDR1_D21
DDR1_D[23:16]
DDR1_D23
DDR1_CLK1N
DDR1_D[7:0]
D DR1_A[13:0]
DDR1_CLK0N
DDR1_CLK0
+VREF_DDR
DDR1_D[15:8]
GND
GND
GND
GND
+1V8
+1V8
DDR1_DQS1P
DDR1_DQS1N
DDR1_DQM1
DDR1_DQM0
DDR1_DQM2
DDR1_DQS0N
DDR1_DQM3
DDR1_DQS0P
DDR1_DQS3N
DDR1_DQS3P
DDR1_DQS2P
DDR1_DQS2N
DDR1_ODT23
DDR1_ODT01
DDR1_CKE
DDR1_BA1
DDR1_BA2
DDR1_BA0
DDR1_CLK1
DDR1_CLK1N
DDR1_CASN
DDR1_WEN
DDR1_RASN
DDR1_CS0N
DDR1_CS1N
DDR1_CLK0
DDR1_CLK0N
+VREF_DDR
DDR1_D[15:8]
DDR1_D[7:0]
DDR1_A[13:0]
DDR1_D[31:24]
DDR1_D[23:16]
DDR1_A[13:0]
_
_
(CLUSTER)
(CLUSTER)
5- DDR2 clock and DQS P/N traces must be routed as 100 Ohms Differential pairs. Traces width and gap according to PCB stackup.
4- Length of all Data signals between Byte Lane should be matched together (<400 mils).
BCM7440 DDR2 2x16 --> Design notes and Layout Guidelines:
1- Place 121 ohms clock termination at the end of the differencial trace.
2- Pin swaping can only be done on data lines inside each group of 8 bit (Byte Lane).
3- Length of all Data signals into a Byte Lane should be matched together (<100 mils).
1- Place 121 ohms clock termination at the end of the differencial trace.
2- Pin swaping can only be done on data lines inside each group of 8 bit (Byte Lane).
3- Length of all Data signals into a Byte Lane should be matched together (<100 mils).
6- When developing the PCB floor plan, the proximity of the DDR2 device to the memory controller is an important factor.
- To avoid the use of external address termination on high-speed DDR2, the address trace length should be less than 2.5in.
* If those requirements can not be reached, refer to JEDEC JESD79-2B standard for design rules and terminations.
* If those requirements can not be reached, refer to JEDEC JESD79-2B standard for design rules and terminations.
DDR2 BANK-1
DDR2-1L
DDR2-1H
121
R571
2
1
DDR2
64Mx16
FBGA 84
HYB18TC1G160CF-2.5
U18
BGA84
NC2
E2
NC1
A2
WE*
K3
VDD5
J9
VDD4
R1
VDD3
M9
VDD2
E1
VDD1
A1
VDDQ10
G9
VDDQ9
G7
VDDQ8
G1
VDDQ7
E9
VDDQ6
G3
VDDQ5
C9
VDDQ4
C7
VDDQ3
C3
VDDQ2
C1
VDDQ1
A9
VDDL
J1
A12
R2
A11
P7
RFU/A13
R8
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A2
M7
A1
M3
A0
M8
BA2
L1
BA1
L3
BA0
L2
CK
J8
CK*
K8
VREF
J2
CKE
K2
CS*
L8
RAS*
K7
CAS*
L7
ODT
K9
DQ15
B9
DQ14
B1
DQ13
D9
DQ12
D1
DQ11
D3
DQ10
D7
DQ9
C2
DQ8
C8
DQ7
F9
DQ6
F1
DQ5
H9
DQ4
H1
DQ3
H3
DQ2
H7
DQ1
G2
DQ0
G8
UDM
B3
LDM
F3
UDQS
B7
UDQS*/NU
A8
LDQS
F7
LDQS*/NU
E8
VSS5
P9
VSS4
N1
VSS3
J3
VSS2
E3
VSS1
A3
VSSQ10
H8
VSSQ9
H2
VSSQ8
F8
VSSQ7
F2
VSSQ6
E7
VSSQ5
D8
VSSQ4
D2
VSSQ3
B8
VSSQ2
B2
VSSQ1
A7
VSSDL
J7
RFU/A14
R3
RFU/A15
R7
DDR2
64Mx16
FBGA 84
HYB18TC1G160CF-2.5
U17
BGA84
NC2
E2
NC1
A2
WE*
K3
VDD5
J9
VDD4
R1
VDD3
M9
VDD2
E1
VDD1
A1
VDDQ10
G9
VDDQ9
G7
VDDQ8
G1
VDDQ7
E9
VDDQ6
G3
VDDQ5
C9
VDDQ4
C7
VDDQ3
C3
VDDQ2
C1
VDDQ1
A9
VDDL
J1
A12
R2
A11
P7
RFU/A13
R8
A10/AP
M2
A9
P3
A8
P8
A7
P2
A6
N7
A5
N3
A4
N8
A3
N2
A2
M7
A1
M3
A0
M8
BA2
L1
BA1
L3
BA0
L2
CK
J8
CK*
K8
VREF
J2
CKE
K2
CS*
L8
RAS*
K7
CAS*
L7
ODT
K9
DQ15
B9
DQ14
B1
DQ13
D9
DQ12
D1
DQ11
D3
DQ10
D7
DQ9
C2
DQ8
C8
DQ7
F9
DQ6
F1
DQ5
H9
DQ4
H1
DQ3
H3
DQ2
H7
DQ1
G2
DQ0
G8
UDM
B3
LDM
F3
UDQS
B7
UDQS*/NU
A8
LDQS
F7
LDQS*/NU
E8
VSS5
P9
VSS4
N1
VSS3
J3
VSS2
E3
VSS1
A3
VSSQ10
H8
VSSQ9
H2
VSSQ8
F8
VSSQ7
F2
VSSQ6
E7
VSSQ5
D8
VSSQ4
D2
VSSQ3
B8
VSSQ2
B2
VSSQ1
A7
VSSDL
J7
RFU/A14
R3
RFU/A15
R7
121
R572
2
1
0.1UF
C659
1
2
0.1UF
C656
1
2
0.1UF
C653
1
2
0.1UF
C652
1
2
0.1UF
C654
1
2
0.1UF
C655
1
2
0.1UF
C657
1
2
22UF
C658
1
2
22UF
C651
1
2
0.1UF
C669
1
2
0.1UF
C664
1
2
0.1UF
C667
1
2
0.1UF
C663
1
2
0.1UF
C668
1
2
0.1UF
C666
1
2
0.1UF
C665
1
2
22UF
C670
1
2
22UF
C662
1
2
Main Board Electric Diagram: DDR2 BANK-1
45
harman/kardon
BDP 1 / BDP 10 Service Manual
EBI_~DS
EBI_~WE0
NAND_WPN
NAND_R~B
EBI_~RD
E BI_~TS
NAND_CEN
EBI_~CS1
EBI_~CS0
EBI_D1
EBI_D0
EBI_D4
EBI_D3
EBI_D2
EBI_D[7:0]
EBI_D7
EBI_D6
EBI_D5
N AND_CE2
GND
GND
+3V3
+3V3
+3V3
+3V3
+3V3
EBI_R~W
EBI_~WE1
EBI_~CS0
EBI_~RD
EBI_~CS1
NAND_R~B
EBI_~DS
EBI _~TS
EBI_~WE0
EBI_A25
EBI_D[7:0]
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
-------
PCI_~GNT0
EBI_DATA5
EBI_~CS2
-------
-------
EBI_~CS5
-------
-------
PCI_~REQ3
PCI_~REQ2
PCI_~REQ1
PCI_~REQ0
PCI_~GNT3
PCI_~GNT2
PCI_~GNT1
PCI_INT_A1
PCI_INT_A0
EBI_~CS3
EBI_~CS1
EBI_~CS0
NAND_CE0
NAND_RE
-------
-------
NAND_WE
-------
NAND_CLE
EBI_~TS
-------
-------
-------
-------
-------
-------
-------
PCI_CLK_IN
PCI_~RST
PCI_INT_A2
PCI_AD5
EBI_~RD
EBI_~WE1
EBI_~WE0
EBI_~TSIZE1
EBI_~TSIZE0
EBI_~TA2
EBI_~DS
NAND_ALE
-------
-------
EBI_R~W
NAND_CE1
NAND_I/O5
EBI_ADDR25
EBI_ADDR14
EBI_ADDR13
EBI_ADDR12
EBI_ADDR11
-------
PCI_AD27
EBI_ADDR10
-------
PCI_AD26
EBI_ADDR9
-------
PCI_AD25
EBI_ADDR8
-------
PCI_AD24
EBI_ADDR7
-------
PCI_AD23
EBI_ADDR6
-------
PCI_AD22
-------
-------
-------
-------
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
-------
-------
EBI_ADDR5
-------
PCI_AD21
EBI_ADDR4
-------
PCI_AD20
EBI_ADDR3
-------
PCI_AD19
EBI_ADDR2
-------
PCI_AD18
EBI_ADDR1
-------
PCI_AD17
EBI_ADDR0
-------
PCI_AD16
EBI_DATA15
-------
PCI_AD15
EBI_DATA14
-------
PCI_AD14
EBI_DATA13
-------
PCI_AD13
EBI_DATA12
-------
PCI_AD12
EBI_DATA11
-------
PCI_AD11
EBI_DATA10
-------
PCI_AD10
EBI_DATA9
-------
PCI_AD9
EBI_DATA8
-------
PCI_AD8
NAND_I/O7
PCI_AD7
EBI_DATA6
NAND_I/O6
PCI_AD6
EBI_DATA4
NAND_I/O4
PCI_AD4
EBI_DATA3
NAND_I/O3
PCI_AD3
EBI_DATA2
NAND_I/O2
PCI_AD2
NAND_I/O1
PCI_AD1
EBI_DATA0
NAND_I/O0
PCI_AD0
EBI_ADDR19
-------
PCI_~CBE03
EBI_ADDR18
-------
PCI_~CBE02
EBI_ADDR17
-------
PCI_~CBE01
EBI_ADDR16
-------
PCI_~CBE00
EBI_ADDR20
-------
PCI_PAR
-------
-------
PCI_~FRAME
EBI_~TA
-------
PCI_~TDRY
EBI_ADDR21
-------
PCI_~IRDY
-------
PCI_~STOP
EBI_ADDR23
-------
PCI_~DEVSEL
EBI_~TEA
-------
PCI_~SERR
-------
-------
PCI_~PERR
EBI_~CS4
EBI
PCI
NAND
EBI_ADDR22
EBI_DATA7
EBI_DATA1
NAND
NAND_R~B
-------
EBI_ADDR24
-------
EBI_ADDR15
NAND
(CLUSTER)
0.1UF
C609
1
2
22UF
C59
1
2
4.64K
R551
2
1
0
R80
2
1
4.64K
R550
2
1
NAND FLASH
1Gx8
8Gbit
N AND08GW 3B2AN6E
T SO P48
U 15
AL
17
CL
16
I/O7
44
NC_E2*
10
NC_E3*
14
NC_E4*
15
PRE
38
R/B1*
7
NC_R/B2*
6
NC_R/B3*
5
NC_R/B4*
4
NC0
1
NC1
2
NC7
23
NC9
25
NC10
26
NC11
27
NC13
33
NC14
34
NC15
35
NC16
39
NC2
3
NC17
40
NC19
46
NC20
47
NC21
48
NC3
11
NC4
20
NC5
21
NC6
22
VDD0
12
VDD1
37
VSS0
13
VSS1
36
I/O0
29
I/O1
30
I/O2
31
I/O3
32
I/O4
41
I/O5
42
I/O6
43
NC18
45
E1*
9
R*
8
W*
18
WP*
19
NC8
24
NC12
28
4.64K
R553
2
1
4.64K
R552
100MW
1%
2
1
Main Board Electric Diagram: NAND
46
harman/kardon
BDP 1 / BDP 10 Service Manual
BSC_M1_SCL
BSC_M1_SDA
HDMI_CEC
HDMI_PWR
HDMI
_
CE
C
_
F
E
T
-G
1080P_HDMI_HTPLG
1080P_HDMI_DATA2_P
1080P_HDMI_DATA2_N
1080P_HDMI_CLK_N
1080P_HDMI_SDA
1080P_HDMI_SCL
9134_PVCC2
9134_PVCC1
9134_EXT_SWING
HDMI_CEC_A
H DMI_7440_~PWR_FAULT
9134_~INT
RESET _OUT
I2S_T_DATA0
I2S_T_DATA1
I2S_T_DATA2
I2S_T_DATA3
AUD_FS_CLK_0_A
AU D1_SPDIF
I2S_T_C LK
I2S_T_LR
DVO_DE
D VO_HSYNC
DVO_VSYNC
DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11
DVO_D12
DVO_D13
DVO_D14
DVO_D15
DVO_D16
DVO_D17
DVO_D18
DVO_D19
DVO_D20
DVO_D21
DVO_D22
DVO_D23
1080P_HDMI_DATA0_P
1080P_HDMI_DATA0_N
1080P_HDMI_CLK_P
1080P_HDMI_DATA1_N
1080P_HDMI_DATA1_P
DVO_CLK_P
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
+5V
+1V8
+1V8
+1V8
+1V8
+5V
+5V
+3V3
+3V3
+3V3
+3V3
+3V3
+1V8
GND
GND
I2S_T_DATA0
I2S_T_DATA1
I2S_T_DATA2
I2S_T_DATA3
AUD_FS_CLK_0_A
AUD1_SPDIF
I2 S_T_CLK
I2 S_T_LR
DVO_CLK_P
DVO_DE
DVO_HSYNC
DVO_VSYNC
DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11
DVO_D12
DVO_D13
DVO_D14
DVO_D15
DVO_D16
DVO_D17
DVO_D18
DVO_D19
DVO_D20
DVO_D21
DVO_D22
DVO_D23
BSC_M1_SCL
BSC_M1_SDA
9134_~INT
HDMI_7440_~PWR_FAULT
9134_~INT
HDMI_CEC
RESET_OUT
*Noise measured at this point
(CLUSTER)
(CLUSTER)
I2C ADDR:76h/W
77h/R
I2C ADDR:A0h/W
A1h/R
(CLUSTER)
DVO, SIL9134, HDMI
9134
4- Use minimum number of VIA.
3- Route differential pairs above the GND plane. Do not split the GND plane under differential pairs.
2- Match trace lenght of P/N differential pairs. 20 mils max within a pair and 100 mils max between pairs.
1- HDMI Data and clockP/N traces must be routed as 100 Ohms Differential pairs. Traces width and gap according to PCB stackup.
HDMI --> Design notes and Layout Guidelines:
5- When possible, use higher clearance distance between differantials pairs and any others traces (>15 mils).
6- If higher than 2KV protection is necessary on HDMI port use low capacitance ESD protections close to the HDMI connector.
7- Consider limiting current to Maximum 500mA on HDMI 5V power.
6- If higher than 2KV protection is necessary on HDMI port use low capacitance ESD protections close to the HDMI connector.
7- Consider limiting current to Maximum 500mA on HDMI 5V power.
HDMI
ࡴ 2008.5.19
ҹࠡЎ5VA
47PF/NC
C10
1
2
TV S5
INA-1KV
100K/NC
R9
100MW
1%
1%
2
1
0.1UF
C8
1
2
25.5K/NC
R13
2
1
TV S1
INA-1KV
0.1UF
C524
1
2
1.5K
R501
100MW
1%
2
1
FPF2100
SOT23-5
U4
FLAGB
4
GND
2
ON
3
VIN
1
OUT
5
4.64K
R14
100MW
1%
2
1
SIL9134CTU
TQFP100
U3
GND5
100
GND4
87
GND3
65
GND2
54
GND1
13
AGND5
43
AGND4
41
AGND3
35
AGND2
29
AGND1
26
TXC-
30
TXC+
31
TX2-
39
TX2+
40
TX1-
36
TX1+
37
TX0-
33
TX0+
34
HPD
51
DSDA
47
DSCL
46
EXT_SWING
27
DDCPWR5V
45
AVCC33
44
IOVCC33-4
89
IOVCC33-3
66
IOVCC33-2
53
IOVCC33-1
14
AVCC18-2
38
AVCC18-1
32
PVCC2
42
PVCC1
28
CVCC18-5
99
CVCC18-4
76
CVCC18-3
64
CVCC18-2
55
INT
24
RSVDL
52
CI2CA
50
CSDA
49
CSCL
48
DCLK
15
DR3
22
DL3
23
DR2
20
DL2
21
DR1
18
DL1
19
DR0
16
DL0
17
D35
56
D34
57
D33
58
D32
59
D31
60
D30
61
D29
62
D28
63
D27
67
D26
68
D25
69
D24
70
D23
71
D22
72
D21
73
D20
74
D19
75
D18
77
D17
78
D16
79
D15
80
D14
81
D13
82
D12
83
D11
84
D10
85
D9
86
D8
90
D7
91
D6
92
D5
93
D4
94
D3
95
D2
96
D1
97
D0
98
IDCK
88
VSYNC
3
HSYNC
2
DE
1
WS
10
SCK
11
SPDIF
4
MCLK
5
SD3
6
SD2
7
SD1
8
SD0
9
CVCC18-1
12
RESET*
25
47.5K
R528
2
1
100Ohms
L500
1
2
TV S6
INA-1KV
1.5K
R527
2
1
33
R717
2
1
1.5K
R526
2
1
1.5K
R512
2
1
698
R513
100MW
1%
2
1
1.5K
R500
100MW
1%
2
1
100Ohms
L501
1
2
TV S7
INA-1KV
0.1UF
C501
1
2
47UF
C527
1
2
TV S2
INA-1KV
0.1UF
C530
1
2
0.1UF
C503
1
2
47UF
C502
1
2
0.1UF
C535
1
2
10UF/10V
C536
1
2
47UF
C532
1
2
0.1UF
C533
1
2
TV S8
INA-1KV
0.1UF
C539
1
2
0.1UF
C537
1
2
0.1UF
C531
1
2
0.1UF
C500
1
2
TV S3
INA-1KV
0.1UF
C504
1
2
0.1UF
C526
1
2
0.1UF
C540
1
2
0.1UF
C528
1
2
0.1UF
C538
1
2
0.1UF
C529
1
2
TV S4
INA-1KV
HDMI CONNECTOR
500254-1931
J3
MTG3
22
MTG2
21
MTG1
20
MTG4
23
HOT_PLUG_DETECT
19
5V_SUPPLY
18
DDC/CEC_GROUND
17
SDA
16
SCL
15
RESERVED
14
CEC
13
TMDS_DATA_CLK_N
12
TMDS_DATA_CLK_SHIELD
11
TMDS_DATA_CLK_P
10
TMDS_DATA_0_N
9
TMDS_DATA_0_SHIELD
8
TMDS_DATA_0_P
7
TMDS_DATA_1_N
6
TMDS_DATA_1_SHIELD
5
TMDS_DATA_1_P
4
TMDS_DATA_2_N
3
TMDS_DATA_2_SHIELD
2
TMDS_DATA_2_P
1
Q6
PMBF170/NC
g
d
s
Main Board Electric Diagram: DVO, SIL9134, HDMI
47
harman/kardon
BDP 1 / BDP 10 Service Manual
I2S_0_CLOCK
DVO_CLK_P
DVO_D7
DVO_D5
DVO_D6
DVO_D3
DVO_D4
DVO_D0
DVO_D2
E BI_~TS
EBI_~DS
EBI_~TSIZE1
AU D0_SPDIF
U SB0_PWRON
EBI_R~W
EBI_A25
I2S_0_DATA1
I2S_0_DATA0
I2S_0_DATA2
EBI_~WE0
EBI_~WE1
I2S_0_DATA3
I2S_0_LR
+2V5_BCM7440
I2S_S_DATA
DVO_D1
E BI_~TSIZE0
EBI_~RD
U SB1_PWRON
GND
GND
GND
GND
GND
GND
GND
GND
GND
+3V3
+3V3
+1V8
+1V2
EBI_~RD
EBI_~WE1
EBI_~DS
DVO_D0
EBI _~TS
DVO_D2
DVO_D1
DVO_D4
DVO_D3
DVO_D6
DVO_CLK_P
DVO_D5
DVO_D7
+2V5_BCM7440
I2S_0_CLOCK
I2S_0_LR
AUD0_SPDIF
I 2S_0_DATA0
I 2S_0_DATA1
I 2S_0_DATA2
I2 S_0_DATA3
EBI_R~W
EBI_A25
USB0_PWRON
EBI_~TSIZE1
E BI_~TSIZE0
EBI_~W E0
I2S _S_DATA
USB1_PWRON
3: DDR2 Controller Manual Initialization
2: DDR2 bank 0 size = 256/512 MB
1: DDR2 bank 0 size = 128 MB
0: DDR2 bank 0 size = 64 MB
strap_ebi_boot_memory
1
(CLUSTER)
SOC
(CLUSTER)
1- Note these configuration resistors do not need to be close to the BCM7440. So, place them at the destination of the trace.
It will clear the BCM7440 area and help the chip layout.
Boot strap option --> Design notes and Layout Guidelines:
strap_ebi_invert_addr
strap_nand_flash
strap_NMI_polarity
strap_ebi_cs_swap
strap_reset_ext_mode
strap_test_debug_en_1
strap_test_debug_en_0
strap_ddr2_0_size_1
strap_ddr2_0_size_0
strap_ddr2_1_size_1
strap_ddr2_1_size_0
strap_ddr2_mhz_1
strap_ddr2_mhz_0
strap_system_big_endian
strap_pci_client
strap_pci_memwin1_en
strap_pci_memwin2_en
strap_pci_memwin_size_0
strap_pci_memwin_size_1
strap_reset_outb_def_value
strap_xtal_adj3
strap_xtal_adj2
strap_xtal_adj1
strap_xtal_adj0
strap_ebi_rom_size1
strap_ebi_rom_size0
strap_33_27_MHZ_clock
0
0
0
0
strap_nand_flash
strap_NMI_polarity
strap_ebi_cs_swap
strap_reset_ext_mode
strap_test_debug_en_1
strap_reset_ext_mode
strap_test_debug_en_1
strap_ddr2_0_size_1
strap_ddr2_0_size_0
strap_ddr2_1_size_1
strap_ddr2_1_size_0
strap_ddr2_0_size_0
strap_ddr2_1_size_1
strap_ddr2_1_size_0
strap_test_debug_en_0
strap_ddr2_mhz_1
strap_ddr2_mhz_0
strap_spi_slave_enable
strap_ebi_boot_memory
strap_system_big_endian
strap_pci_client
strap_pci_memwin1_en
strap_pci_memwin2_en
strap_pci_memwin_size_1
strap_pci_memwin_size_0
strap_33_27_MHZ_clock
strap_reset_outb_def_value
strap_xtal_adj3
strap_xtal_adj2
strap_xtal_adj1
strap_xtal_adj0
strap_ddr2_mhz_0
strap_spi_slave_enable
strap_ebi_boot_memory
strap_system_big_endian
strap_pci_client
strap_pci_memwin1_en
strap_pci_memwin2_en
strap_pci_memwin_size_1
strap_pci_memwin_size_0
strap_33_27_MHZ_clock
strap_reset_outb_def_value
strap_xtal_adj3
strap_xtal_adj2
strap_xtal_adj1
strap_xtal_adj0
Adjust the 54MHz oscillator bias current
strap_ebi_rom_size1
strap_ebi_rom_size0
strap_ebi_rom_size0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Boot Strap Options
1
0
1
under chip.
BCM7440 Power
BOOTSTRAP
1
0
1: Invert upper bits of EBI address
0: Do not invert EBI address
1: External NAND FLASH present
1: External NAND FLASH present
0: External NOR FLASH present
1: High-active interrupt
0: Low-active interrupt
1: Swap CS_0 and CS_1 signals
0: No swap
1: Swap CS_0 and CS_1 signals
0: No swap
strap_ebi_invert_addr
0: DDR2 bank 0 size = 64 MB
1: DDR2 bank 0 size = 128 MB
2: DDR2 bank 0 size = 256/512 MB
3: DDR2 Controller Manual Initialization
0: DDR2 Banks = 200/400 MHZ
1: DDR2 Banks = 266/533 MHZ
2: DDR2 Banks = 333/667 MHZ
3: DDR2 Banks = 400/800 MHZ
1: SPI slave port configured
0: BSC slave port configured
0: Boot Flash = 8 bits
1: Boot Flash = 16 bits
0: System is little endian
1: System is big endian
1: PCI in client (slave) mode
0: PCI in bridge (master) mode
0: PCI memwin 1 disable
1: PCI memwin 1 enable
0: PCI memwin 2 disable
1: PCI memwin 2 enable
2: 128 MByte window
1: 64 MByte window
3: 256 MByte window
0: 32 MByte window
1: 33 MHz clock output
1: 33 MHz clock output
0: 27 MHz clock output
1: NOR: 16 MBytes NAND: Ebable ECC
0: NOR 64 MBytes NAND: Ebable ECC
0: NOR 64 MBytes NAND: Ebable ECC
2: NOR: 8 MBytes NAND: Disable ECC
3: NOR: 4 MBytes NAND: Disable ECC
int Fix.
Place 4.7uF directly
0
2008.5.19
1.5K
R514
100MW
1%
2
1
22UF
C56
1
2
1.5K
R39
100MW
1%
2
1
0.1UF
C612
1
2
0.1UF
C628
1
2
0.1UF
C34
1
2
0.1UF
C629
1
2
47UF
C581
1
2
0.1UF
C660
1
2
1.5K
R29
100MW
1%
2
1
4.64K
R63
100MW
1%
2
1
4.64K
R516
100MW
1%
DEPOP
2
1
22UF
C534
1
2
0.1UF
C541
1
2
1.5K
R65
100MW
1%
2
1
22UF
C672
1
2
0.1UF
C583
1
2
0.1UF
C646
1
2
0.1UF
C648
1
2
0.1UF
C69
1
2
1.5K
R28
100MW
1%
2
1
4.64K
R518
100MW
1%
DEPOP
2
1
22UF
C613
1
2
0.1UF
C57
1
2
1.5K
R38
100MW
1%
2
1
22UF
C50
1
2
0.1UF
C574
1
2
0.1UF
C584
1
2
4.64K
R519
100MW
1%
2
1
4.64K
R61
100MW
1%
2
1
0.1UF
C51
1
2
1.5K
R66
100MW
1%
2
1
4.7UF
C619
1
2
22UF
C36
1
2
4.64K
R523
100MW
1%
2
1
0.1UF
C43
1
2
0.1UF
C625
1
2
22UF
C627
1
2
1.5K
R520
100MW
1%
2
1
0.1UF
C42
1
2
0.1UF
C54
1
2
1.5K
R36
100MW
1%
2
1
4.7UF
C620
1
2
0.1UF
C641
1
2
4.64K
R517
100MW
1%
2
1
0.1UF
C572
1
2
1.5K
R67
100MW
1%
2
1
0.1UF
C615
1
2
4.7UF
C623
1
2
10UF/10V
C616
1
2
0.1UF
C58
1
2
4.64K
R521
100MW
1%
2
1
4.7UF
C618
1
2
1.5K
R515
100MW
1%
2
1
0.1UF
C606
1
2
0.1UF
C611
1
2
1.5K
R30
100MW
1%
2
1
0.1UF
C621
1
2
0.1UF
C53
1
2
4.64K
R525
100MW
1%
2
1
22UF
C671
1
2
0.1UF
C614
1
2
0.1UF
C636
1
2
1.5K
R522
100MW
1%
DEPOP
2
1
4.64K
R60
100MW
1%
2
1
0.1UF
C588
1
2
0.1UF
C65
1
2
1.5K
R62
100MW
1%
2
1
1.5K
R541
100MW
1%
2
1
0.1UF
C610
1
2
0.1UF
C525
1
2
0.1UF
C33
1
2
0.1UF
C587
1
2
22UF
C66
1
2
0.1UF
C70
1
2
1.5K
R34
100MW
1%
2
1
22UF
C68
1
2
0.1UF
C585
1
2
0.1UF
C55
1
2
4.64K
R64
100MW
1%
2
1
22UF
C67
1
2
4.64K
R529
100MW
1%
2
1
22UF
C52
1
2
0.1UF
C647
1
2
1.5K
R40
100MW
1%
2
1
4.64K
R32
100MW
1%
DEPOP
2
1
22UF
C35
1
2
0.1UF
C586
1
2
0.1UF
C661
1
2
4.64K
R59
100MW
1%
2
1
4.64K
R524
100MW
1%
2
1
47UF
C547
1
2
0.1UF
C617
1
2
Main Board Electric Diagram: BOOT STRAP OPTIONS & BCM7440B
48
harman/kardon
BDP 1 / BDP 10 Service Manual
Click on the first or last page to see other BDP 10 service manuals if exist.