Harman Kardon AVR 70 Service Manual ▷ View online
3
18
Renesas Technology Corp.
Doc. No.
RCS-R2A15218FP-650
Rev.
Page
/
C.S
Integrated Circuit (R2A15218FP)
1
Fig 2. PIN DESCRIPTION
PIN No.
Name
Function
49
DATA
Input pin of control data
50
CLOCK
Input pin of control clock
Output pin of FL/FR/C/SW/SL/SR/SBL/SBR channel
FRIN2, FLIN2,
SRN2,SLIN2,
SWIN2,CIN2,
SBRIN2,SBLIN2
SRN2,SLIN2,
SWIN2,CIN2,
SBRIN2,SBLIN2
43,42,
41,40,
39,38,
37,36
41,40,
39,38,
37,36
Input pin of L/R/C/SW/SL/SR/SBL/SBR channel (Multi IN 1/2)
Output pin for L/R channel REC Output
Frequency characteristic setting pin of L/R channel tone control (Treble)
28,34
TREL, TRER
26,27,
32,33
32,33
23,21,
17,15,
11,9,
5,3
17,15,
11,9,
5,3
FROUT,FLOUT,
COUT,SWOUT,
SROUT, SLOUT,
SBROUT,SBLOUT
COUT,SWOUT,
SROUT, SLOUT,
SBROUT,SBLOUT
BASSL1,BASSL2
BASSR1,BASSR2
BASSR1,BASSR2
FLIN1, FRIN1,
CIN1,SWIN1,
SLIN1,SRIN1,
SBLIN1,SBRIN1
CIN1,SWIN1,
SLIN1,SRIN1,
SBLIN1,SBRIN1
93,94,
95,96,
97,98,
99,100
95,96,
97,98,
99,100
Frequency characteristic setting pin of L/R channel tone control (Bass)
24,20,
18,14,
12,8,
6,2
18,14,
12,8,
6,2
FRC,FLC,
CC,SWC,
SRC,SLC,
SBRC,SBLC
CC,SWC,
SRC,SLC,
SBRC,SBLC
Connects capacitor for reducing click noise of
L/R/C/SW/SL/SR/SBL/SBR channel volume
INL1,INL2, INL3,
INL4,INL5,INL6,
INL7,INL8,INL9
INL4,INL5,INL6,
INL7,INL8,INL9
Input pin of L/R channel (Input Selector)
59,61,63,
65,67,69,
71,73,79
65,67,69,
71,73,79
INR1,INR2, INR3,
INR4,INR5,INR6,
INR7,INR8,INR9
INR4,INR5,INR6,
INR7,INR8,INR9
58,60,62,
64,66,68,
70,72,78
64,66,68,
70,72,78
54,55
ADCL, ADCR
Output pin for L/R channel ADC
90,91
4,7,10,16,
19,22,56
19,22,56
AGND
Analog ground of internal circuit
30
AVCC
Positive power supply to internal circuit
48
DGND
Digital ground of internal circuit
52
AVEE
Negative power supply to internal circuit
46,47
SUBL,SUBR
Output pin for L/R channel SUB Output
RECR3,RECL3
51
MUTE
Outside Mute Control PIN
75,76,
81,82,
83,84,
85,86
81,82,
83,84,
85,86
INRA/RECR1,INLA/RECL1,
INRB/RECR2,INLB/RECL2,
INR10/RECR4,INL10/RECL4,
INR11/RECR5,INL11/RECL5
Input pin of L/R channel (Input Selector)/
Output pin for L/R channel REC Output
Output pin for L/R channel REC Output
N.C.
1,13,25,29,31,
35,53,
57,74,77,80,
87,88,89,92
35,53,
57,74,77,80,
87,88,89,92
No Connected PIN
44,45
SBRCIN,SBLCIN
Input pin for SBL/SBR channel Volume
[AK4588]
MS0287-J-03
2009/05
- 3 -
■
ブロック図
Input
Selector
Clock
Recovery
Clock
Generator
DAIF
Decoder
AC-3/MPEG
Detect
DEM
μP I/F
Audio
I/F
X'tal
Oscillator
PDN
INT0
LRCK2
BICK2
SDTO2
DAUX2
MCKO2
XTO
XTI
R
PVDD
PVSS
CDTI
CDTO
CCLK
CSN
DVDD
DVSS
TVDD
MCKO1
I2C
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DIT
TX0
Error &
Detect
STATUS
INT1
Q-subcode
buffer
TX1
B,C,U,
VOUT
8 to 3
VIN
Audio
I/F
LPF
LPF
LPF
LPF
LPF
LPF
LOUT1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
DAC
DATT
DEM
ADC
HPF
ADC
HPF
RIN
LIN
LRCK1
BICK1
SDTI1
SDTI2
SDTI3
DAUX1
MCLK
LRCK
BICK
SDOUT
SDIN1
SDIN2
SDIN3
SDIN2
SDIN3
MCLK
SDTO1
Format
Converter
SDTI4
SDIN4
LPF
LPF
LOUT4
ROUT4
DAC
DATT
DEM
DAC
DATT
DEM
DAC
DATT
DEM
DAC
DATT
DEM
DAC
DATT
DEM
DAC
DATT
DEM
DAC
DATT
DEM
AVDD
AVSS
[AK4588]
MS0287-J-03
2009/05
- 4 -
■
オーダリングガイド
AK4588VQ -40
∼ +85°C 80pin
LQFP(0.5mm
pitch)
AKD4588
評価ボード
■
ピン配置
(Top View)
IN
T
1
BO
U
T
TV
D
D
DV
D
D
D
VSS
XT
O
XTI
TE
ST
3
MCK
O
2
MCK
O
1
CO
UT
UO
UT
VO
U
T
SD
T
O
2
BI
C
K
2
L
RCK
2
SD
T
O
1
BI
C
K
1
L
RCK
1
CD
T
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
RX2
NC
RX3
PVSS
R
PVDD
RX4
TEST2
RX5
CAD0
RX6
CAD1
RX7
I2C
DAUX2
VIN
MCLK
TX0
TX1
TX1
INT0
NC
LOUT3
NC
ROUT4
NC
LOUT4
DZF1
DZF2
MASTER
PDN
XTL0
XTL1
SDTI1
SDTI2
SDTI3
SDTI4
DAUX1
CSN
CDTI/SDA
CCLK/SCL
LOUT3
NC
ROUT4
NC
LOUT4
DZF1
DZF2
MASTER
PDN
XTL0
XTL1
SDTI1
SDTI2
SDTI3
SDTI4
DAUX1
CSN
CDTI/SDA
CCLK/SCL
TE
ST
1
RX
1
NC
RX
0
AV
S
S
A
V
DD
VR
E
F
H
VCO
M
RI
N
LI
N
NC
RO
UT1
NC
LO
U
T
1
NC
RO
UT2
NC
LO
U
T
2
NC
RO
UT3
[AK4588]
MS0287-J-03
2009/05
- 6 -
ピン／機能
No. Pin
Name
I/O
Function
1
INT1
O
Interrupt 1 Pin
2
BOUT O
Block-Start Output Pin for Receiver Input
“H” during first 40 flames.
3 TVDD
- Output Buffer Power Supply Pin, 2.7V
∼5.5V
4 DVDD
- Digital Power Supply Pin, 4.5V
∼5.5V
5
DVSS
-
Digital Ground Pin
6
XTO
O
X'tal clock Output Pin
7
XTI
I
X'tal / External clock Input Pin
8 TEST3
I
Test 3 Pin
This pin should be connected to DVSS.
9
MCKO2
O
Master Clock Output 2 Pin
10
MCKO1
O
Master Clock Output 1 Pin
11 COUT
O C-bit
Output Pin for Receiver Input
12
UOUT
O
U-bit Output Pin for Receiver Input
13
VOUT
O
V-bit Output Pin for Receiver Input
14
SDTO2
O
Audio Serial Data Output Pin (DIR/DIT part)
15
BICK2
I/O
Audio Serial Data Clock Pin (DIR/DIT part)
16
LRCK2
I/O
Channel Clock Pin (DIR/DIT part)
17
SDTO1
O
Audio Serial Data Output Pin (ADC/DAC part)
18
BICK1
I/O
Audio Serial Data Clock Pin (ADC/DAC part)
19
LRCK1
I/O
Input Channel Clock Pin
20
CDTO
O
Control Data Output Pin in Serial Mode, I2C pin= “L”.
CCLK
I
Control Data Clock Pin in Serial Mode, I2C pin= “L”
21
SCL
I
Control Data Clock Pin in Serial Mode, I2C pin= “H”
CDTI
I
Control Data Input Pin in Serial Mode, I2C pin= “L”.
22
SDA
I/O
Control Data Pin in Serial Mode, I2C pin= “H”.
I
Chip Select Pin in Serial Mode, I2C pin=”L”.
23 CSN
I
This pin should be connected to DVSS, I2C pin=”H”.
24
DAUX1
I
AUX Audio Serial Data Input Pin (ADC/DAC part)
25
SDTI4
I
DAC4 Audio Serial Data Input Pin
26
SDTI3
I
DAC3 Audio Serial Data Input Pin
27
SDTI2
I
DAC2 Audio Serial Data Input Pin
28
SDTI1
I
DAC1 Audio Serial Data Input Pin
29
XTL1
I
X’tal Frequency Select 0 Pin
30
XTL0
I
X’tal Frequency Select 1 Pin
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