Harman Kardon AVR 360 (serv.man5) Service Manual ▷ View online
SN74ALVCH16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES041C – JULY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 20-bit noninverting buffer/driver is designed
for 1.65-V to 3.6-V V
for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16827 is composed of two 10-bit
sections with separate output-enable signals. For
either 10-bit buffer section, the two output-enable
(1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must
both be low for the corresponding Y outputs to be
active. If either output-enable input is high, the
outputs of that 10-bit buffer section are in the
high-impedance state.
sections with separate output-enable signals. For
either 10-bit buffer section, the two output-enable
(1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must
both be low for the corresponding Y outputs to be
active. If either output-enable input is high, the
outputs of that 10-bit buffer section are in the
high-impedance state.
To ensure the high-impedance state during power
up or power down, OE should be tied to V
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
unused or floating data inputs at a valid logic level.
The SN74ALVCH16827 is characterized for
operation from –40
operation from –40
°
C to 85
°
C.
Copyright
1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE1
1Y1
1Y2
1Y2
GND
1Y3
1Y4
1Y4
V
CC
1Y5
1Y6
1Y7
1Y6
1Y7
GND
1Y8
1Y9
1Y9
1Y10
2Y1
2Y2
2Y3
2Y2
2Y3
GND
2Y4
2Y5
2Y6
2Y5
2Y6
V
CC
2Y7
2Y8
2Y8
GND
2Y9
2Y10
2OE1
1OE2
1A1
1A2
GND
1A3
1A4
V
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2A9
2A10
2OE2
2A8
GND
2A9
2A10
2OE2
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
harman/kardon
AVR 360/230 Service Manual
Page 89 of 138
TC7MZ4051,4052,4053FK
2001-10-23
2
Pin Assignment
(top view)
Truth Table
Control Inputs
“ON” Channel
Inhibit C* B A
MZ4051FK
MZ4052FK
MZ4053FK
L L L L
0
0X,
0Y
0X,
0Y,
0Z
L
L
L
H
1
1X, 1Y
1X, 0Y, 0Z
L
L
H
L
2
2X, 2Y
0X, 1Y, 0Z
L
L
H
H
3
3X, 3Y
1X, 1Y, 0Z
L H L L
4
¾
0X, 0Y, 1Z
L H L H
5
¾
1X, 0Y, 1Z
L H H L
6
¾
0X, 1Y, 1Z
L H H H
7
¾
1X, 1Y, 1Z
H X X X None None None
X: Don't care, *: Except MZ4052FK
1
14
0
3
A
B
C
13
12
11
10
9
15
4 1
2
3
4
5
6
7
6
COM
7
5
INH
V
EE
2
8
16
GND
V
CC
TC7MZ4051FK
1X
14
X-COM
0X
3X
A
B
13
12
11
10
9
15
0Y 1
2
3
4
5
6
7
2Y
Y-COM
3Y
1Y
INH
V
EE
2X
8
16
GND
V
CC
TC7MZ4052FK
X-COM
14
1X
0X
A
B
C
13
12
11
10
9
15
1Y 1
2
3
4
5
6
7
0Y
1Z
Z-COM
0Z
INH
V
EE
Y-COM
8
16
GND
V
CC
TC7MZ4053FK
harman/kardon
AVR 360/230 Service Manual
Page 90 of 138
TC74HC4094AP/AF/AFN
2007-10-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC4094AP,TC74HC4094AF,TC74HC4094AFN
8-Bit Shift and Store Register (3-state)
The TC74HC4094A is a high speed CMOS 8-BIT SHIFT AND
STROBE REGISTER fabricated with silicon gate C
2
MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It consists of an 8-bit shift register and an 8-bit latch with
3-state output buffers. Data is shifted serially though the shift
register on the positive going transition of the CK input. The
output of the last stage (Qs) can be used to cascade several
devices. Data on the Qs output is transferred to a second output
(Q’s) on the following negative transition of the CK input. The
data in each stage of the shift register is provided to a
corresponding latch, on the negative going transition of the
STROBE input. When STROBE is held high, data propagates
through the latch to a 3-state output buffer. This buffer is
enabled when OUTPUT ENABLE input is set high.
register on the positive going transition of the CK input. The
output of the last stage (Qs) can be used to cascade several
devices. Data on the Qs output is transferred to a second output
(Q’s) on the following negative transition of the CK input. The
data in each stage of the shift register is provided to a
corresponding latch, on the negative going transition of the
STROBE input. When STROBE is held high, data propagates
through the latch to a 3-state output buffer. This buffer is
enabled when OUTPUT ENABLE input is set high.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: f
max
= 73 MHz (typ.) at V
CC
= 5 V
• Low power dissipation: I
CC
= 4 μA (max) at Ta = 25°C
• High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
• Output drive capability: 10 LSTTL loads
• Symmetrical output impedance: |I
• Symmetrical output impedance: |I
OH
|
= I
OL
= 4 mA (min)
•
Balanced propagation delays: t
pLH
∼
− t
pHL
• Wide operating voltage range: V
CC
(opr)
= 2 to 6 V
• Pin and function compatible with 4094B
Pin Assignment
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC4094AP
TC74HC4094AF
TC74HC4094AFN
Weight
DIP16-P-300-2.54A
DIP16-P-300-2.54A
: 1.00 g (typ.)
SOP16-P-300-1.27A
: 0.18 g (typ.)
SOL16-P-150-1.27
: 0.13 g (typ.)
harman/kardon
AVR 360/230 Service Manual
Page 91 of 138
harman/kardon
AVR 360/230 Service Manual
Page 92 of 138
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