Harman Kardon AVR 139 (serv.man4) Service Manual ▷ View online
1/26
January 2005
M24C64
M24C32
M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
■
Two-Wire I
2
C Serial Interface
Supports 400kHz Protocol
■
Single Supply Voltage:
–
–
4.5 to 5.5V for M24Cxx
–
2.5 to 5.5V for M24Cxx-W
–
1.8 to 5.5V for M24Cxx-R
■
Write Control Input
■
BYTE and PAGE WRITE (up to 32 Bytes)
■
RANDOM and SEQUENTIAL READ Modes
■
Self-Timed Programming Cycle
■
Automatic Address Incrementing
■
Enhanced ESD/Latch-Up Protection
■
More than 1 Million Erase/Write Cycles
■
More than 40-Year Data Retention
Table 1. Product List
Figure 1. Packages
Reference
Part Number
M24C64
M24C64
M24C64-W
M24C64-R
M24C32
M24C32
M24C32-W
M24C32-R
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2x3mm² (MLP)
harman/kardon
AVR 139-141-142/230 Service Manual
Page 61 of 83
M24C64, M24C32
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SUMMARY DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
Figure 2. Logic Diagram
I
2
C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in
Table 3.
), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 2. Signal Names
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V
CC
has reached
the Power On Reset (POR) threshold voltage, and
all operations are disabled – the device will not re-
spond to any command. In the same way, when
V
all operations are disabled – the device will not re-
spond to any command. In the same way, when
V
CC
drops from the operating voltage, below the
Power On Reset (POR) threshold voltage, all op-
erations are disabled and the device will not re-
spond to any command.
A stable and valid V
erations are disabled and the device will not re-
spond to any command.
A stable and valid V
CC
(as defined in
Table 9.
and
Table 10.
) must be applied before applying any
logic signal.
Figure 3. DIP, SO, TSSOP and UFDFPN
Connections
Connections
Note: See
PACKAGE MECHANICAL
section for package dimen-
sions, and how to identify pin-1.
AI01844B
3
E0-E2
SDA
VCC
M24C64
M24C32
M24C32
WC
SCL
VSS
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
SDA
VSS
SCL
WC
E1
E0
VCC
E2
AI01845C
M24C64
M24C32
M24C32
1
2
3
4
8
7
6
5
harman/kardon
AVR 139-141-142/230 Service Manual
Page 62 of 83
T5CC1
2. Pin Assignment and Pin Functions
The assignment of input/output pins for the T5CC1, their names and functions are as follows:
2.1 Pin Assignment Diagram
Figure 2.1.1 shows the pin assignment of the T5CC1.
DVSS 91
P66 90
85 P62/SI/SCL
86 P63/INT0
87 P64/SCOUT
88 P65
DVCC 89
P52/AN2 94
P51/AN1 93
P50/AN0 92
P55/AN5 97
P54/AN4 96
P53/AN3/ADTRG 95
VREFH
100
P57/AN7 99
P56/AN6 98
AVCC 3
AVSS 2
Top view
QFP100
VREFL 1
P72/TA3OUT 6
P71/TA1OUT 5
P70/TA0IN 4
P75/TA7OUT 9
P74/TA5OUT 8
P73/TA4IN 7
P82/TB0OUT0 12
P81/TB0IN1/INT6 11
P80/TB0IN0/INT5 10
P85/TB1IN1/INT8 15
P84/TB1IN0/INT7 14
P83/TB0OUT1 13
P90/TXD0 18
P87/TB1OUT1 17
P86/TB1OUT0 16
P93/TXD1 21
P92/SCLK0/CTS0 20
P91/RXD0 19
DVCC 25
AM0 24
P95/SCLK1/CTS1 23
P94/RXD1 22
X2 26
AM1 29
X1 28
DVSS 27
P97/XT2 32
P96/XT1 31
RESET 30
PA2/INT3 37
PA1/INT2 36
PA0/INT1 35
EMU1 34
EMU0 33
81 P42/CS2
82 P43/CS3
83 P60/SCK
84 P61/SO/SDA
80
P41/CS1
76 P35/BUSAK
77 P36/R/W
78 P37/BOOT
79 P40/CS0
72 P31/WR
73 P32/HWR
74 P33/WAIT
75 P34/BUSRQ
68 P25/A5/A21
69 P26/A6/A22
70 P27/A7/A23
71 P30/RD
64 DVCC
65 P22/A2/A18
66 P23/A3/A19
67 P24/A4/A20
60 P20/A0/A16
61 P21/A1/A17
62 DVSS
63 NMI
58 P16/AD14/A14
59 P17/AD15/A15
54 P12/AD10/A10
55 P13/AD11/A11
56 P14/AD12/A12
57 P15/AD13/A13
49 P05/AD5
48 P04/AD4
50 P06/AD6
51 P07/AD7
52 P10/AD8/A8
53 P11/AD9/A9
46 P02/AD2
45 P01/AD1
47 P03/AD3
43 ALE
42 PA7
44 P00/AD0
40 PA5
38 PA3/INT4
39 PA4
41 PA6
Figure 2.1.1 Pin assignment diagram (100-pin LQFP)
T5CC1
2006-03-03
harman/kardon
AVR 139-141-142/230 Service Manual
Page 63 of 83
T5CC1
2.2 Pin Names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2.1 Pin names and functions.
Table 2.2.1 Pin names and functions (1/3)
Pin Name
Number
of Pins
I/O Functions
P00
∼P07
AD0
∼AD7
8 I/O
I/O
Port 0: I/O port that allows I/O to be selected at the bit level
Address and data (lower): Bits 0 to 7 of address and data bus
Address and data (lower): Bits 0 to 7 of address and data bus
P10
∼P17
AD8
∼AD15
A8
∼A15
8 I/O
I/O
Output
Port 1: I/O port that allows I/O to be selected at the bit level
Address and data (upper): Bits 8 to 15 for address and data bus
Address: Bits 8 to 15 of address bus
Address and data (upper): Bits 8 to 15 for address and data bus
Address: Bits 8 to 15 of address bus
P20
∼P27
A0
∼A7
A16
∼A23
8 I/O
Output
Output
Output
Port 2: I/O port that allows I/O to be selected at the bit level
Address: Bits 0 to 7 of address bus
Address: Bits 16 to 23 of address bus
Address: Bits 0 to 7 of address bus
Address: Bits 16 to 23 of address bus
P30
RD
1 Output
Output
Port 30: Output port
Read: Strobe signal for reading external memory
This port output RD signal also case of reading internal-area by setting P3
<P30>
Read: Strobe signal for reading external memory
This port output RD signal also case of reading internal-area by setting P3
<P30>
= 0 and P3FC <P30F> = 1.
P31
WR
1 Output
Output
Port 31: Output port
Write: Strobe signal for writing data to pins AD0 to AD7
Write: Strobe signal for writing data to pins AD0 to AD7
P32
HWR
1 I/O
Output
Port 32: I/O port (with pull-up resistor)
High Write: Strobe signal for writing data to pins AD8 to AD15
High Write: Strobe signal for writing data to pins AD8 to AD15
P33
WAIT
1 I/O
Input
Port 33: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait
((1+N) WAIT mode)
Wait: Pin used to request CPU bus wait
((1+N) WAIT mode)
P34
BUSRQ
1 I/O
Input
Port 34: I/O port (with pull-up resistor)
Bus Request: Signal used to request Bus Release
Bus Request: Signal used to request Bus Release
P35
BUSAK
1 I/O
Output
Port 35: I/O port (with pull-up resistor)
Bus Acknowledge: Signal used to acknowledge Bus Release
Bus Acknowledge: Signal used to acknowledge Bus Release
P36
W
/
R
1 I/O
Output
Port 36: I/O port (with pull-up resistor)
Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle.
Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle.
P37
BOOT
BOOT
1 I/O
Input
Port 36: I/O port (with pull-up resistor)
This pin sets single boot mode.
When released reset, Single boot mode is started at P37＝Low level.
This pin sets single boot mode.
When released reset, Single boot mode is started at P37＝Low level.
P40
CS0
1 I/O
Output
Port 40: I/O port (with pull-up resistor)
Chip Select 0: Outputs 0 when address is within specified address area
Chip Select 0: Outputs 0 when address is within specified address area
P41
CS1
1 I/O
Output
Port 41: I/O port (with pull-up resistor)
Chip Select 1: Outputs 0 if address is within specified address area
Chip Select 1: Outputs 0 if address is within specified address area
P42
CS2
1 I/O
Output
Port 42: I/O port (with pull-up resistor)
Chip Select 2: Outputs 0 if address is within specified address area
Chip Select 2: Outputs 0 if address is within specified address area
P43
CS3
1 I/O
Output
Port 43: I/O port (with pull-up resistor)
Chip Select 3: Outputs 0 if address is within specified address area
Chip Select 3: Outputs 0 if address is within specified address area
P50
∼P57
AN0
∼AN7
ADTRG
8 Input
Input
Input
Input
Port 5: Pin used to input port
Analog input: Pin used to input to AD converter
AD Trigger: Signal used to request start of AD converter (Shared with53 pin)
Analog input: Pin used to input to AD converter
AD Trigger: Signal used to request start of AD converter (Shared with53 pin)
T5CC1
2006-03-03
harman/kardon
AVR 139-141-142/230 Service Manual
Page 64 of 83
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