Harman Kardon AVR 135 (serv.man3) Service Manual ▷ View online
PIN No.
Pin Name
I/O
Function
1,12,23
+VD1
-
Digital Power supply. Normally +2.5v
2,13,24
DGND
-
Digital Ground
3
AUD3
O
SPDIF transmitter output/Digital audio output(N.C)
4
WR
I
Host write strobe pin(connected to GND with an external resistor)
5
RD
I
Host parallel output enable pin(pulled up with an external resistor)
6
CS_DA
I
SPI Serial data input pin
7
CS_CK
I
Serial control clock input pin
8
EMAD7
I/O
9
EMAD6
I/O
10
EMAD5
I/O
11
EMAD4
I/O
Serial data IN/OUTPUT pins(pulled up with an external resistor)
14
EMAD3
I/O
15
EMAD2
I/O
16
EMAD1
I/O
17
EMAD0
I/O
18
CS_CE
I
Host parallel chip select pin
19
SCDIO(AK_DOUT)
O
Serial control port data ouput pin
20
INTREQ
O
Control port interrupt request output pin
21
EXTMEM
I/O
External Memory Chip Selector(pulled up with an external resistor)
22
SDATAN1(SDI)
I
PCM audio data input number 1 pin
25
SCLKN1(BICK)
I
PCM audio input bit clock pin
26
LRCLKN1(LRCK)
I
PCM audio input sample rate clock pin
27
CMPDAT(SDI)
I
PCM audio data input number 2 pin
28
CMPCLK(BICK)
I
PCM audio input bit clock pin
29
CREQ(LRCK)
I
PCM audio input sample rate clock pin
30
CLKIN(XIN)
I
Master clock input(used external clock)
31
CLKSEL(GND)
I
DSP clock mode select pin: connect the GND
32
FILT1
Connects to an external filter for the on-chip phase-locked loop
33
FILT1
Connects to an external filter for the on-chip phase-locked loop
34
+2.5V
-
Analog Power supply for clock generator . Normally +2.5V
35
AGND
-
Analog ground supply for clock generator PLL.
36
RESET(CS_RST)
I
Master reset input pin
37
DBDATA
-
Reserved pin and should be pulled up with an external resistor.
38
DBCLK
-
Reserved pin and should be pulled up with an external resistor.
39
AUD2(SDO2)
O
PCM multi-format digital-audio data ouput2 pin
40
AUD1(SDO1)
O
PCM multi-format digital-audio data ouput1 pin
41
AUD0(SDO0)
O
PCM multi-format digital-audio data ouput0 pin
42
LRCLK
I
Audio output sample rate clock pin
43
SCLK(BICK)
I
Audio ouput bit clock pin
44
MCLK
I
Audio master clock output pin
AUDIO DSP (CS493263 - CLG : IC75)
CMPDAT
SDATAN2
SDATAN2
CMPCLK
SCLKN2
SCLKN2
CMPREQ
LRCLKN2
LRCLKN2
SCLKN1
STCCLK2
STCCLK2
LRCLKN1
SDATAN1
CLKIN
CLKSEL
FILTD
FILTS
VA
AGND
DGND(3:1)
VD(3:1)
XMT95
AUDA
LRCLK
SCLK
MCLK
DC
DD
EXTMEM.
GPIO8
A800T
INTERQ
A1,
SCDIN
A0,
SCCLK
CS
STC
Parallel or Serial Host Interface
RESET
SCDIO,
SCDOUT,
PSEL,
GPIO9
WR,
DR,
EMWR,
GPIO10
RD,
R/W,
EMOE,
GPIO11
DATA7:0,
EMAD7:0,
GPIO7:0
Compressed
Data Input
Interface
RAM
Program
Memory
ROM
Program
Memory
RAM
Data
Memory
RAM
Output
Buffer
Output
Formatter
ROM
Data
Memory
PLL
Clock Manager
RAM Input
Buffer
24-Bit
DSP Processing
Digital
Audio
Input
Interface
Framer
Shifter
Input
Buffer
Controller
PIN ASSIGNMENT.(CS493263)
(TOP VIEW)
BlOCK DIAGRAM(CS493263)
VD1
DGND1
AUDATA3, XMT958
WR,DS,EMWR,GPIO10
RD,R/W,EMOE,GPIO11
A1,SCDIN
A0,SCCLK
DATA7,EMAD7,GPIO7
CS493XXX-CLG
44-pin PLCC
Top View
DATA6,EMAD6,GPIO6
DATA5,EMAD5,GPIO5
DATA4,EMAD4,GPIO4
DATA3,EMAD3,GPIO3
DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1
DATA0,EMAD0,GPIO0
VD2
DGND2
CS
SCDIO,SCDOUT,PSEL,GPIO9
ABOOT,INTREQ
EXTMEM,GPIO8
SDATAN1
MCLK
SCLK
LRCLK
AUDATA0
SCLK
LRCLK
AUDATA0
AUDATA1
AUDATA2
DC
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
6
5 4
3
2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
DD
RESET
AGND
FILT2
CLKSEL
CLKIN
CMPREQ,LRCLKN2
VA
FILT1
CMPDAT,SCLKN2,RCV958
CMPCLK,SCLKN2
LRCLKN1
VD3
SCLKN1,STCCLK2
DGND3
DGND3
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