Harman Kardon AVR 135 (serv.man3) Service Manual ▷ View online
14
OPERATION
FIG. 1 Block Diagram
Operation Diagram
Step 1. Output Voltage is equal to Power Source Voltage (V
DD
).
Step 2. When Input Voltage to Comparator reaches the state of Vref
≥
V
DD
·(Rb+Rc)/(Ra+Rb+Rc)at Point A (Detected Voltage –V
DET
), the output of Com-
parator is reserved, so that Output Voltage becomes GND.
Step 3. In the case of CMOS Output, Output Voltage becomes unstable when Supply Voltage (V
DD
) is smaller than Minimum Operating Voltage. In the
case of Nch Open Drain Output, a pulled-up voltage is output.
Step 4. Output Voltage becomes equal to GND.
Step 5. When Input Voltage to Comparator reaches the state of Vref
≤
V
DD
· (Rb)/(Ra+ Rb) at Point B (Released Voltage +V
DET
), the output of Comparator is reversed,
so that Output Voltage becomes equal to Supply Voltage (V
DD
).
FIG. 2 Operation Diagram
Step
Step 1
Step 2
Step 3
Step 4
Step 5
Comparator(+) Pin
Input Voltage
I
II
II
II
I
Comparator Output
H
L
Indefinite
L
H
Tr. 1
OFF
ON
Indefinite
ON
OFF
Output Tr.
Pch
ON
OFF
Indefinite
OFF
ON
Nch
OFF
ON
Indefinite
ON
OFF
I
.
Rb + Rc
Ra + Rb + Rc
·V
DD
II.
Rb
Ra + Rb
·V
DD
GND
OUT
V
DD
Ra
Rb
Rc
Tr.1
Vref
Pch
Nch
–
+
Detector Threshold Hysteresis
t
PLH
1
2
3
4
5
A
B
• In R
×
5VT
××
A, Nch Tr. drain is
connected to OUT pin.
• In R
×
5VT
××
C, Nch Tr. drain
and Pch Tr. drain are connected
to OUT pin.
Released Volage +V
DET
Supply Volage
Detected Volage –V
DET
(V
DD
)
Minimum Operating Volage
GND
Output Volage
(OUT)
GND
R
×
5VL
2
BLOCK DIAGRAMS
•
Nch Open Drain Output (R
×
5VL
××
A)
•
CMOS Output (R
×
5VL
××
C)
TIME CHART
DEFINITION OF OUTPUT DELAY TIME t
PLH
2
3
Vref
OUT
GND
V
DD
–
+
1
V
DD
2
1
3
Vref
OUT
GND
–
+
Detector Threshold Hysteresis
t
PLH
Released Voltage
+V
DET
Detected Voltage
–V
DET
Supply Voltage
(V
(V
DD
)
Output Voltage
(OUT)
(OUT)
Minimum Operating Voltage
GND
GND
GND
t
PLH
t
PHL
Input Voltage
(V
(V
DD
)
Output Voltage
Nch Open Drain Output
GND
GND
3.5V
7.0V
1.2V
+V
DET
+ 2.0V
t
PLH
t
PHL
CMOS Output
GND
GND
1.2V
+V
DET
+ 2.0V
+V
DET
+2.0V
+V
DET
+ 2.0V
2
Input Voltage
(V
(V
DD
)
Output Voltage
•
TO-92
PIN CONFIGURATION
•
SOT-89
•
SOT-23-5
PIN DESCRIPTION
•
TO-92
•
SOT-89
•
SOT-23-5
Pin No
Symbol
1
OUT
2
V
DD
3
GND
4
NC
5
NC
Pin No
Symbol
1
OUT
2
V
DD
3
GND
Pin No
Symbol
1
OUT
2
V
DD
3
GND
1
2
3
(mark side)
1
2
3
(mark side)
1
2
3
(mark side)
5
4
R
×
5VL
5
R
×
5VL
14
OPERATION
FIG. 1 Block Diagram
Operation Diagram
Step 1. Output Voltage is equal to Power Source Voltage (V
DD
).
Step 2. When Input Voltage to Comparator reaches the state of Vref
≥
V
DD
·(Rb+Rc)/(Ra+Rb+Rc)at Point A (Detected Voltage –V
DET
), the output of Com-
parator is reserved, so that Output Voltage becomes GND.
Step 3. In the case of CMOS Output, Output Voltage becomes unstable when Supply Voltage (V
DD
) is smaller than Minimum Operating Voltage. In the
case of Nch Open Drain Output, a pulled-up voltage is output.
Step 4. Output Voltage becomes equal to GND.
Step 5. When Input Voltage to Comparator reaches the state of Vref
≤
V
DD
·(Rb)/(Ra+Rb) at Point B (Released Voltage +V
DET
), the output of Comparator is reserved,
so that Output Voltage becomes equal to Supply Voltage (V
DD
)
FIG. 2 Operation Diagram
Step
Step 1
Step 2
Step 3
Step 4
Step 5
Comparator(+)Pin
Input Voltage
I
II
II
II
I
Comparator Output
H
L
Indefinite
L
H
Tr. 1
OFF
ON
Indefinite
ON
OFF
Output Tr.
Pch
ON
OFF
Indefinite
OFF
ON
Nch
OFF
ON
Indefinite
ON
OFF
I.
Rb
+
Rc
Ra
+
Rb
+
Rc
·V
DD
II.
Rb
Ra
+
Rb
·V
DD
GND
OUT
V
DD
Ra
Rb
Rc
Tr.1
Vref
Pch
Nch
–
+
Detector Threshold Hysteresis
t
PLH
1
2
3
4
5
A
B
· In R
×
5VL
××
A, Nch Tr. drain is con-
nected to OUT pin.
· In R
×
5VL
××
C, Nch Tr. drain and
Pch Tr. drain are connected to
OUT pin.
Released Volage +V
DET
Supply Volage
Detected Volage –V
DET
(V
DD
)
Minimum Operating Volage
GND
Output Volage
(OUT)
GND
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