Sony BDP-S790 Service Manual ▷ View online
BDP-S790
T3
RA9_B
O
Memory address bit 9
6-6
AG17
RCLK0
O
Memory clock 0 possitive
AH17
RCLK0_
O
Memory clock 0 negative
AG6
RCLK1
O
Memory clock 1 possitive
AH6
RCLK1_
O
Memory clock 1 negative
AF13
RCS_
O
Memory chip select
AE13
RCSX_
O
Memory chip select
AG14
RDQ0
I/O
Memory data bit 0
AF15
RDQ1
I/O
Memory data bit 1
AH14
RDQ2
I/O
Memory data bit 2
AF14
RDQ3
I/O
Memory data bit 3
AG20
RDQ4
I/O
Memory data bit 4
AF20
RDQ5
I/O
Memory data bit 5
AH20
RDQ6
I/O
Memory data bit 6
AG19
RDQ7
I/O
Memory data bit 7
AD16
RDQ8
I/O
Memory data bit 8
AF16
RDQ9
I/O
Memory data bit 9
AC17
RDQ10
I/O
Memory data bit 10
AE16
RDQ11
I/O
Memory data bit 11
AD17
RDQ12
I/O
Memory data bit 12
AE18
RDQ13
I/O
Memory data bit 13
AD18
RDQ14
I/O
Memory data bit 14
AC18
RDQ15
I/O
Memory data bit 15
AG2
RDQ16
I/O
Memory data bit 16
AG1
RDQ17
I/O
Memory data bit 17
AH1
RDQ18
I/O
Memory data bit 18
AH2
RDQ19
I/O
Memory data bit 19
AF8
RDQ20
I/O
Memory data bit 20
AG8
RDQ21
I/O
Memory data bit 21
AF9
RDQ22
I/O
Memory data bit 22
AH8
RDQ23
I/O
Memory data bit 23
AH3
RDQ24
I/O
Memory data bit 24
AF4
RDQ25
I/O
Memory data bit 25
AG3
RDQ26
I/O
Memory data bit 26
AG4
RDQ27
I/O
Memory data bit 27
AF6
RDQ28
I/O
Memory data bit 28
AE6
RDQ29
I/O
Memory data bit 29
AE8
RDQ30
I/O
Memory data bit 30
AE7
RDQ31
I/O
Memory data bit 31
AH19
RDQM0
I/O
Memory data mask bit 0
AE17
RDQM1
I/O
Memory data mask bit 1
AC8
RDQM2
I/O
Memory data mask bit 2
AH4
RDQM3
I/O
Memory data mask bit 3
AG16
RDQS0
I/O
Memory positive data strobe bit 0
AH16
RDQS0_
I/O
Memory negative data strobe bit 0
AH18
RDQS1
I/O
Memory positive data strobe bit 1
AG18
RDQS1_
I/O
Memory negative data strobe bit 1
AG5
RDQS2
I/O
Memory positive data strobe bit 2
AH5
RDQS2_
I/O
Memory negative data strobe bit 2
AH7
RDQS3
I/O
Memory positive data strobe bit 3
AG7
RDQS3_
I/O
Memory negative data strobe bit 3
AE10
RODT
O
Memory on die termination enable
AE11
RRAS_
O
Memory row address strobe
AC7
DDRVREFF_C
I
Memory VREF
AA15
DDRVREFF_D
I
Memory VREF
AE9
RWE_
O
Memory write enable
AD9
RRESET
O
Memory reset
Dram Channel B
R1
RA0_B
O
Memory address bit 0
V5
RA1_B
O
Memory address bit 1
T2
RA2_B
O
Memory address bit 2
U4
RA3_B
O
Memory address bit 3
T5
RA4_B
O
Memory address bit 4
U3
RA5_B
O
Memory address bit 5
R3
RA6_B
O
Memory address bit 6
T1
RA7_B
O
Memory address bit 7
R4
RA8_B
O
Memory address bit 8
BDP-S790
6-7
W6
RA10_B
O
Memory address bit 10
U5
RA11_B
O
Memory address bit 11
V6
RA12_B
O
Memory address bit 12
N4
RA13_B
O
Memory address bit 13
T6
RA14_B
O
Memory address bit 14
P5
RBA0_B
O
Memory bank address bit 0
U6
RBA1_B
O
Memory bank address bit 1
N5
RBA2_B
O
Memory bank address bit 2
R5
RCAS__B
O
Memory column address strobe
V2
RCKE_B
O
Memory clock enable
AB2
RCLK0_B
O
Memory clock 0 possitive
AB1
RCLK0__B
O
Memory clock 0 negative
M2
RCLK1_B
O
Memory clock 1 possitive
M1
RCLK1__B
O
Memory clock 1 negative
V3
RCS_B
O
Memory chip select
V4
RCSX_B
O
Memory chip select
W1
RDQ0_B
I/O
Memory data bit 0
Y3
RDQ1_B
I/O
Memory data bit 1
W2
RDQ2_B
I/O
Memory data bit 2
AA3
RDQ3_B
I/O
Memory data bit 3
AE3
RDQ4_B
I/O
Memory data bit 4
AF3
RDQ5_B
I/O
Memory data bit 5
AD2
RDQ6_B
I/O
Memory data bit 6
AD3
RDQ7_B
I/O
Memory data bit 7
W4
RDQ8_B
I/O
Memory data bit 8
W5
RDQ9_B
I/O
Memory data bit 9
Y4
RDQ10_B
I/O
Memory data bit 10
AA4
RDQ11_B
I/O
Memory data bit 11
AB4
RDQ12_B
I/O
Memory data bit 12
AB6
RDQ13_B
I/O
Memory data bit 13
AB5
RDQ14_B
I/O
Memory data bit 14
AA6
RDQ15_B
I/O
Memory data bit 15
J2
RDQ16_B
I/O
Memory data bit 16
J1
RDQ17_B
I/O
Memory data bit 17
K1
RDQ18_B
I/O
Memory data bit 18
K20
RDQ19_B
I/O
Memory data bit 19
R2
RDQ20_B
I/O
Memory data bit 20
N3
RDQ21_B
I/O
Memory data bit 21
P3
RDQ22_B
I/O
Memory data bit 22
P4
RDQ23_B
I/O
Memory data bit 23
J4
RDQ24_B
I/O
Memory data bit 24
J5
RDQ25_B
I/O
Memory data bit 25
J6
RDQ26_B
I/O
Memory data bit 26
J3
RDQ27_B
I/O
Memory data bit 27
L4
RDQ28_B
I/O
Memory data bit 28
L3
RDQ29_B
I/O
Memory data bit 29
M5
RDQ30_B
I/O
Memory data bit 30
M6
RDQ31_B
I/O
Memory data bit 31
AD1
RDQM0_B
O
Memory data mask bit 0
AA5
RDQM1_B
O
Memory data mask bit 1
K3
RDQM2_B
O
Memory data mask bit 2
K4
RDQM3_B
O
Memory data mask bit 3
AA2
RDQS0_B
I/O
Memory positive data strobe bit 0
AA1
RDQS0_B
I/O
Memory negative data strobe bit 0
AC1
RDQS1_B
I/O
Memory positive data strobe bit 1
AC2
RDQS1_B
I/O
Memory negative data strobe bit 1
L2
RDQS2_B
I/O
Memory positive data strobe bit 2
L1
RDQS2_B
I/O
Memory negative data strobe bit 2
N1
RDQS3_B
I/O
Memory positive data strobe bit 3
N2
RDQS3_B
I/O
Memory negative data strobe bit 3
P6
RODT_B
O
Memory on die termination enable
V1
RRAS__B
O
Memory row address strobe
N8
DDRVREF_A
I
Memory VREF
V8
DDRVREF_B
I
Memory VREF
N6
RWE__B
O
Memory write enable
T4
RRESET_B
O
Memory reset
BDP-S790
Output
FEFMO
B11
6-8
E6
AVDD33_USB_P0P1
Power
3.3V Analog power for USB
Y26
AVDD33_USB_P2
Power
3.3V Analog power for USB
F12
AVSS33_USB_P0P1
Ground
Analog ground for USB
Y22
AVSS33_USB_P2
Ground
Analog ground for USB
B5
USB_DM_P0
Analog
USB port0 differential serial data bus (minus)
A5
USB_DP_P0
Analog
USB port0 differential serial data bus (plus)
B4
USB_DM_P1
Analog
USB port1 differential serial data bus (minus)
A4
USB_DP_P1
Analog
USB port1 differential serial data bus (plus)
AA28
USB_DM_P2
Analog
USB port2 differential serial data bus (minus)
AA27
USB_DP_P2
Analog
USB port2 differential serial data bus (plus)
A6
USB_VRT
Analog
USB reference resistor
W28
USB_VRT_P2
Analog
USB port2 reference resistor
E-fuse
H1
EFPWRQ
Power
2.5V power for E-fuse programming
Ethernet PHY
AA24
AVDD33_LD
Power
Line driver 3.3V analog power
AA25
AVDD33_COM
Power
PLL/BG 3.3V analog power
AA22
AVSS33_LD
Ground
Line driver analog ground
Y20
AVSS33_COM
Ground
Analog ground
AB28
TXVP_0
Analog
Ethernet TD+
AC28
TXVP_1
Analog
Ethernet RD+
AB27
TXVN_0
Analog
Ethernet TD-
AD27
REXT
Analog
External reference resistor
AC27
TXVN_1
Analog
Ethernet RD-
SERVO
Analog
F20
AGND33_1
Ground
Analog Ground
Analog
G18
AGND33_2
Ground
Analog Ground
Analog
F17
AGND33_3
Ground
Analog Ground
Analog
G21
AGND12_1
Ground
Analog Ground
Analog
F19
AGND12_2
Ground
Analog Ground
Analog
E23
AVDD12_1
Power (1.2V)
Power Pin
Analog
C15
AVDD12_2
Power (1.2V)
Power Pin
Analog
F18
AVDD33_1
Power (3.3V)
Power Pin
Analog
E18
AVDD33_3
Power (3.3V)
Power Pin
Auxiliary Input
E14
E17
FECFREQ
AUX1
Analog I/O
Alternative Function : Signal Monitoring
3.3V LVTTL I/O,
Frequency selection signal output, or LDD serial interface data or 12C
5V-tolerance,
SDA. The pin is spike-free at power-on stage.
Slow slew,
2,4,6,8 mA PDR,
F14
FECMOD
75K pull-up (3.3V)
3.3V LVTTL I/O,
High frequency modulation mode selection signal output, or LDD serial
5V-tolerance,
interface command enable. The pin is spike-free at power-on stage.
Slow slew,
2,4,6,8 mA PDR,
75K pull-down (0V)
Analog
D10
A11
FEEJECT_
FEDMO
Output
Disk motor control output. DAC output.
3.3V LVTTL I/O,
Eject/stop key input, active low. The pin is spike-free at power-on stage.
5V-tolerance,
Alternate function :
6 mA PDR,
General IO.
C9
FEFG
75K pull-up (3.3V)
Motor Hall sensor input. The pin is spike-free at power-on stage.
3.3V LVTTL I/O,
5V-tolerance,
6 mA PDR,
75K pull-up (3.3V)
Feed motor 1 control. DAC output.
Analog
USB
BDP-S790
Analog
Analog
Alternate function: Internal monitored signal output/ General output.
6-9
Feed motor 2 control. DAC output.
Analog
A12
FEFMO2
Output
Feed motor 3 control. DAC output.
B12
FEFMO3
Analog I/O
Alternative Function : Auxiliary servo input
Feed motor 4 control. DAC output.
Feed motor 4 control. DAC output.
C12
FEFMO4
Analog I/O
Alternative Function : Auxiliary servo input
Focus servo output. PDM output of focus servo compensator
Analog
A14
FOO
Output
Laser Power Monitor Input for CD APC/Differential negative input
D21
E21
E21
FPDOCD
FPDODVD
Analog Input
Laser Power Monitor Input for CD APC/Differential positive input
Read gain switch 1
Analog Input
D15
FEGAINSW1
Analog
Read gain switch 2
Output
C13
FEGAINSW2
Analog
Read gain switch 3
Output
C10
D13
FEGIO0
FEGAINSW3
Analog
Output
LDD serial interface data. The pin is spike-free at power-on stage.
3.3V LVTTL I/O,
5V-tolerance,
The pin is not allowed to pull-up in circuit layout.
F13
FEGIO1
2,4,6,8 mA PDR,
General IO
NC
75K pull-down (0V)
3.3V LVTTL I/O,
5V-tolerance,
E10
FEGIO10
2,4,6,8 mA PDR,
75K pull-down (0V)
3.3V LVTTL I/O,
PC RS232 serial receive data. The pin is spike-free at power-on stage.
5V-tolerance,
General IO.
F7
FEGIO11
2,4,6,8 mA PDR,
75K pull-up (3.3V)
3.3V LVTTL I/O,
PC RS232 serial transmit data. The pin is spike-free at power-on stage.
5V-tolerance,
General IO.
E8
FEGIO3
2,4,6,8 mA PDR,
75K pull-up (3.3V)
3.3V LVTTL I/O,
LED Control Output. Initial 0 Output. The pin is spike-free at power-on
5V-tolerance,
stage.
2,4,6,8 mA PDR,
General IO
75K pull-down (0V)
D7
FEGIO4
Analog
Read gain switch 4.
Output
General IO.
E13
FEGIO5
Analog
Read gain switch 5.
Output
General IO.
D9
C7
FEGIO6
FEGIO7
Analog
NC
Output
3.3V LVTTL I/O,
General IO. The pin is spike-free at power-on stage. The pin is not
5V-tolerance,
allowed to pull-up in circuit layout.
D6
FEGIO9
2,4,6,8 mA PDR,
NC
75K pull-down (0V)
3.3V LVTTL I/O,
5V-tolerance,
2,4,6,8 mA PDR,
75K pull-down (0V)
D19
HAVC
Analog
Decoupling Pin for Reference Voltage of Main and Sub Beams
Output
B20
INA
Analog Input
Input of Main Beam Signal (A)
A20
INB
Analog Input
Input of Main Beam Signal (B)
B19
INC
Analog Input
Input of Main Beam Signal (C)
A19
IND
Analog Input
Input of Main Beam Signal (D)
A17
INE
Analog Input
Input of Sub-Beam Signal (E)
D18
INF
Analog Input
Input of Sub-Beam Signal (F)
C19
C18
C18
ING
INH
INH
Analog Input
Input of Sub-Beam Signal (G)
Analog Input
Input of Sub-Beam Signal (H)
Multiplexer Output 1 for Signal Monitoring. The pin is not allowed to pull-up
Multiplexer Output 1 for Signal Monitoring. The pin is not allowed to pull-up
C16
MPXOUT1
Output
in circuit layout.
Alternate function: Internal monitored signal output/ General output.
Multiplexer Output 2 for Signal Monitoring. The pin is not allowed to pull-up
Alternate function: Internal monitored signal output/ General output.
Multiplexer Output 2 for Signal Monitoring. The pin is not allowed to pull-up
C17
MPXOUT2
Output
in circuit layout.
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